time_sim.sdf

实用的程序代码

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "gate_reduce")
  (DATE "Tue Jan  6 18:42:24 1998")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx VERILOG SDF writer")
  (VERSION "M1.4.12")
  (DIVIDER /)
  (VOLTAGE 5.00:5.00:5.00)
  (PROCESS)
  (TEMPERATURE 25.00:25.00:25.00)
  (TIMESCALE 1ps)
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U155)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
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    )
  )
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    (INSTANCE U156)
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      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U157)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
      )
    )
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    (CELLTYPE "X_BUF")
    (INSTANCE U159)
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      (ABSOLUTE
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      )
    )
  )
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    (CELLTYPE "X_BUF")
    (INSTANCE U160)
    (DELAY
      (ABSOLUTE
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    (CELLTYPE "X_BUF")
    (INSTANCE U161)
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      (ABSOLUTE
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    (INSTANCE U164)
    (DELAY
      (ABSOLUTE
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        (IOPATH IN OUT  (1600:1600:1600) (1600:1600:1600))
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    (CELLTYPE "X_INV")
    (INSTANCE U165)
    (DELAY
      (ABSOLUTE
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    (CELLTYPE "X_INV")
    (INSTANCE U166)
    (DELAY
      (ABSOLUTE
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    (CELLTYPE "X_INV")
    (INSTANCE U167)
    (DELAY
      (ABSOLUTE
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    (CELLTYPE "X_INV")
    (INSTANCE U168)
    (DELAY
      (ABSOLUTE
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    (INSTANCE U169)
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      (ABSOLUTE
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        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
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    (CELLTYPE "X_AND2")
    (INSTANCE U170)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (2828:2828:2828) (2828:2828:2828))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U171)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (6759:6759:6759) (6759:6759:6759))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U172)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (2134:2134:2134) (2134:2134:2134))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (2285:2285:2285) (2285:2285:2285))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U173)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1345:1345:1345) (1345:1345:1345))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U174)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1193:1193:1193) (1193:1193:1193))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0\/CLRZERO_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (PORT CLK  (1206:1206:1206) (1206:1206:1206))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (3947:3947:3947) (3947:3947:3947))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U175)
    (DELAY
      (ABSOLUTE
        (PORT IN  (2738:2738:2738) (2738:2738:2738))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U176)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (2203:2203:2203) (2203:2203:2203))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U177)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (2203:2203:2203) (2203:2203:2203))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (990:990:990) (990:990:990))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U179)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U180)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1749:1749:1749) (1749:1749:1749))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U182)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1317:1317:1317) (1317:1317:1317))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0\/ST_INT_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (PORT CLK  (1212:1212:1212) (1212:1212:1212))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (3665:3665:3665) (3665:3665:3665))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U183)
    (DELAY
      (ABSOLUTE
        (PORT IN  (2771:2771:2771) (2771:2771:2771))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U184)
    (DELAY
      (ABSOLUTE
        (PORT IN  (2232:2232:2232) (2232:2232:2232))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U186)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U187)
    (DELAY
      (ABSOLUTE
        (PORT IN  (3052:3052:3052) (3052:3052:3052))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U189)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (1280:1280:1280) (1280:1280:1280))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0\/ECNT_E_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (4738:4738:4738) (4738:4738:4738))
        (PORT CLK  (1194:1194:1194) (1194:1194:1194))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (5906:5906:5906) (5906:5906:5906))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U190)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1745:1745:1745) (1745:1745:1745))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U191)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1745:1745:1745) (1745:1745:1745))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1248:1248:1248) (1248:1248:1248))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U192)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1280:1280:1280) (1280:1280:1280))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1413:1413:1413) (1413:1413:1413))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U193)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U194)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1745:1745:1745) (1745:1745:1745))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U195)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1745:1745:1745) (1745:1745:1745))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1446:1446:1446) (1446:1446:1446))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U196)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1256:1256:1256) (1256:1256:1256))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1708:1708:1708) (1708:1708:1708))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U197)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1\/CLRZERO_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (PORT CLK  (1212:1212:1212) (1212:1212:1212))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (4447:4447:4447) (4447:4447:4447))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U198)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U199)
    (DELAY
      (ABSOLUTE
        (PORT IN  (2738:2738:2738) (2738:2738:2738))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )