time_sim.sdf

实用的程序代码

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "gate_reduce")
  (DATE "Tue Jan  6 18:46:27 1998")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx VERILOG SDF writer")
  (VERSION "M1.4.12")
  (DIVIDER /)
  (VOLTAGE 5.00:5.00:5.00)
  (PROCESS)
  (TEMPERATURE 25.00:25.00:25.00)
  (TIMESCALE 1ps)
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U173)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U174)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U175)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U177)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U178)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U179)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U182)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1403:1403:1403) (1403:1403:1403))
        (IOPATH IN OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U183)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1296:1296:1296) (1296:1296:1296))
        (IOPATH IN OUT  (2420:2420:2420) (2420:2420:2420))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U184)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1242:1242:1242) (1242:1242:1242))
        (IOPATH IN OUT  (2420:2420:2420) (2420:2420:2420))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U185)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1112:1112:1112) (1112:1112:1112))
        (IOPATH IN OUT  (1290:1290:1290) (1290:1290:1290))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0\/CLRZERO_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (PORT CLK  (1212:1212:1212) (1212:1212:1212))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (3598:3598:3598) (3598:3598:3598))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U188)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1665:1665:1665) (1665:1665:1665))
        (IOPATH IN OUT  (1290:1290:1290) (1290:1290:1290))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0\/ST_INT_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (PORT CLK  (1219:1219:1219) (1219:1219:1219))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (3907:3907:3907) (3907:3907:3907))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U191)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (3339:3339:3339) (3339:3339:3339))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1900:1900:1900) (1900:1900:1900))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U193)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (3843:3843:3843) (3843:3843:3843))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1358:1358:1358) (1358:1358:1358))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0\/ECNT_E_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (820:820:820) (820:820:820))
        (PORT CLK  (1206:1206:1206) (1206:1206:1206))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (4158:4158:4158) (4158:4158:4158))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U195)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1420:1420:1420) (1420:1420:1420))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U198)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (1625:1625:1625) (1625:1625:1625))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0\/ZCNT_E_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (820:820:820) (820:820:820))
        (PORT CLK  (1231:1231:1231) (1231:1231:1231))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (4193:4193:4193) (4193:4193:4193))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U199)
    (DELAY
      (ABSOLUTE
        (PORT IN  (2211:2211:2211) (2211:2211:2211))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U201)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (3705:3705:3705) (3705:3705:3705))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U202)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1208:1208:1208) (1208:1208:1208))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_0\/ECNT_reg\<2\>)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (PORT CLK  (1206:1206:1206) (1206:1206:1206))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (4011:4011:4011) (4011:4011:4011))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U204)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1356:1356:1356) (1356:1356:1356))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1420:1420:1420) (1420:1420:1420))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U205)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1420:1420:1420) (1420:1420:1420))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1483:1483:1483) (1483:1483:1483))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U206)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (0:0:0) (0:0:0))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1483:1483:1483) (1483:1483:1483))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U207)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1356:1356:1356) (1356:1356:1356))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U208)
    (DELAY
      (ABSOLUTE
        (PORT IN  (3212:3212:3212) (3212:3212:3212))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U210)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U211)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1727:1727:1727) (1727:1727:1727))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U213)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1263:1263:1263) (1263:1263:1263))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1\/CLRZERO_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (PORT CLK  (1219:1219:1219) (1219:1219:1219))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (3598:3598:3598) (3598:3598:3598))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))
      (SETUP CE (posedge CLK) (0:0:0))
      (SETUP IN (posedge CLK) (0:0:0))
      (HOLD RST (posedge CLK) (0:0:0))
      (HOLD IN (posedge CLK) (0:0:0))
      (HOLD CE (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U214)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1461:1461:1461) (1461:1461:1461))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U215)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1270:1270:1270) (1270:1270:1270))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U216)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (1270:1270:1270) (1270:1270:1270))
        (IOPATH IN0 OUT  (0:0:0) (0:0:0))
        (PORT IN1  (1192:1192:1192) (1192:1192:1192))
        (IOPATH IN1 OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U218)
    (DELAY
      (ABSOLUTE
        (PORT IN  (1481:1481:1481) (1481:1481:1481))
        (IOPATH IN OUT  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE U219)
    (DELAY
      (ABSOLUTE
        (PORT IN0  (2976:2976:2976) (2976:2976:2976))
        (IOPATH IN0 OUT  (1600:1600:1600) (1600:1600:1600))
        (PORT IN1  (0:0:0) (0:0:0))
        (IOPATH IN1 OUT  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE I_1\/ST_INT_reg)
    (DELAY
      (ABSOLUTE
        (PORT IN  (0:0:0) (0:0:0))
        (PORT CLK  (1219:1219:1219) (1219:1219:1219))
        (IOPATH CLK OUT  (2820:2820:2820) (0:0:0))
        (PORT CE  (3956:3956:3956) (3956:3956:3956))
        (IOPATH SET OUT  (0:0:0) (0:0:0))
        (PORT RST  (0:0:0) (0:0:0))
        (IOPATH RST OUT  (0:0:0) (0:0:0))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP RST (posedge CLK) (0:0:0))