time_sim.v

实用的程序代码

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 19:20:57 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module parameter1 (A, B, OP_OUT, OPCODE);
    input A;
    input B;
    output OP_OUT;
    input [1:0] OPCODE;

    wire n106, n107, n108, n109, n131, n130, n128, n129, \U52/$1I20_GTS_TRI , 
    \U54/2_0 , \U55/2_0 , U53_2_INV, U56_2_INV, \U54/n129_2_INV , 
    \U52/$1I20_GTS_TRI_2_INV ;
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U48 (.IN (OPCODE[1]), .OUT (n106));
    X_BUF U49 (.IN (OPCODE[0]), .OUT (n107));
    X_BUF U50 (.IN (A), .OUT (n108));
    X_BUF U51 (.IN (B), .OUT (n109));
    X_AND2 U53 (.IN0 (n128), .IN1 (n106), .OUT (U53_2_INV));
    X_AND2 U56 (.IN0 (n129), .IN1 (n130), .OUT (U56_2_INV));
    X_IPAD \OPCODE<1>_PAD  (.PAD (OPCODE[1]));
    X_IPAD \OPCODE<0>_PAD  (.PAD (OPCODE[0]));
    X_IPAD A_PAD (.PAD (A));
    X_IPAD B_PAD (.PAD (B));
    X_OPAD OP_OUT_PAD (.PAD (OP_OUT));
    X_BUF \U52/$1I20  (.IN (n131), .OUT (\U52/$1I20_GTS_TRI ));
    X_TRI \U52/$1I20_GTS_TRI_21  (.IN (\U52/$1I20_GTS_TRI ), .OUT (OP_OUT), 
    .CTL (\U52/$1I20_GTS_TRI_2_INV ));
    X_AND2 \U54/n129/2_0  (.IN0 (n108), .IN1 (n109), .OUT (\U54/2_0 ));
    X_AND2 \U54/n129  (.IN0 (\U54/2_0 ), .IN1 (n107), .OUT (\U54/n129_2_INV ));
    X_OR2 \U55/n128/2_0  (.IN0 (n108), .IN1 (n109), .OUT (\U55/2_0 ));
    X_OR2 \U55/n128  (.IN0 (\U55/2_0 ), .IN1 (n107), .OUT (n128));
    X_INV U53_2_INV_22 (.IN (U53_2_INV), .OUT (n130));
    X_INV U56_2_INV_23 (.IN (U56_2_INV), .OUT (n131));
    X_INV \U54/n129_2_INV_24  (.IN (\U54/n129_2_INV ), .OUT (n129));
    X_INV \U52/$1I20_GTS_TRI_2_INV_25  (.IN (GTS), .OUT 
    (\U52/$1I20_GTS_TRI_2_INV ));
    X_PD NGD2VER_PD_20 (.OUT (GTS) );
  endmodule