time_sim.tv

实用的程序代码

// VERILOG TestFixture Template produced by ngd2ver M1.4.12
// Design file: time_sim.nga
// Date:Tue Jan  6 19:18:24 1998

// ATTENTION: This file was created by NGD2VER and may therefore be overwritten
// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to
// a new name, or 'paste' this text into another file, to avoid accidental loss
// of data.

`timescale 1 ns/1 ps

module test;
  reg sel;
  wire [7:0] out;
  reg [7:0] a;
  reg [7:0] b;

  reg GTS;
  `define GTS_SIGNAL test.GTS

  parameter2 uut ( .sel (sel) , .out (out) , .a (a) , .b (b) 
);

  initial begin
    $timeformat(-9,3,"ns",12);
    $shm_open("time_sim.shm");
    $shm_probe("AS");
  end

  initial begin
    $display("           T so a b ");
    $display("           i eu [ [ ");
    $display("           m lt 7 7 ");
    $display("           e  [ : : ");
    $display("              7 0 0 ");
    $display("              : ] ] ");
    $display("              0     ");
    $display("              ]     ");
    $monitor("%t",$realtime,, sel, "%h", out, "%h", a, "%h", b );
  end

  initial begin
      `GTS_SIGNAL = 0;
    #100
      sel = 0 ;
      a = 0 ;
      b = 0 ;
    #1000 $stop;
    // #1000 $finish;
  end

endmodule