time_sim.sdf

实用的程序代码

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "GATE_CLOCK2")
  (DATE "Tue Jan  6 16:45:49 1998")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx VHDL SDF writer")
  (VERSION "M1.4.12")
  (DIVIDER /)
  (VOLTAGE 5.00:5.00:5.00)
  (PROCESS "best=1.0:nom=1.0:worst=1.0")
  (TEMPERATURE 25.00:25.00:25.00)
  (TIMESCALE 1ps)
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U35)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U36)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U37)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U39)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (2050:2050:2050) (2050:2050:2050))
      )
    )
  )
  (CELL
    (CELLTYPE "X_FF")
    (INSTANCE OUT1_REG)
    (DELAY
      (ABSOLUTE
        (PORT I  (3015:3015:3015) (3015:3015:3015))
        (PORT CLK  (866:866:866) (866:866:866))
        (IOPATH CLK O  (2820:2820:2820) (2820:2820:2820))
        (PORT CE  (4038:4038:4038) (4038:4038:4038))
        (IOPATH SET O  (2820:2820:2820) (2820:2820:2820))
        (IOPATH RST O  (2820:2820:2820) (2820:2820:2820))
      )
    )
    (TIMINGCHECK
      (WIDTH (posedge CLK)  (4000:4000:4000))
      (WIDTH (negedge CLK)  (4000:4000:4000))
      (SETUP (posedge CE) (posedge CLK) (0:0:0))
      (SETUP (negedge CE) (posedge CLK) (0:0:0))
      (SETUP (posedge I) (posedge CLK) (0:0:0))
      (SETUP (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge RST) (posedge CLK) (0:0:0))
      (HOLD (negedge I) (posedge CLK) (0:0:0))
      (HOLD (negedge CE) (posedge CLK) (0:0:0))
      (HOLD (posedge I) (posedge CLK) (0:0:0))
      (HOLD (posedge CE) (posedge CLK) (0:0:0))
      (WIDTH (posedge RST)  (4000:4000:4000))
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U43)
    (DELAY
      (ABSOLUTE
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_OR2")
    (INSTANCE OUT1_REG_GSR_OR_0)
    (DELAY
      (ABSOLUTE
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U40_1I20)
    (DELAY
      (ABSOLUTE
        (PORT I  (1664:1664:1664) (1664:1664:1664))
        (IOPATH I O  (7300:7300:7300) (7300:7300:7300))
      )
    )
  )
  (CELL
    (CELLTYPE "X_TRI")
    (INSTANCE U40_1I20_GTS_TRI_1)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (0:0:0) (0:0:0))
        (IOPATH CTL O ( )  ( )  (0:0:0) (0:0:0) (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_CKBUF")
    (INSTANCE U38_CLKBUF)
    (DELAY
      (ABSOLUTE
        (PORT I  (2720:2720:2720) (2720:2720:2720))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_BUF")
    (INSTANCE U38_CLKIO_BUF)
    (DELAY
      (ABSOLUTE
        (PORT I  (0:0:0) (0:0:0))
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U41_N_1_2_0)
    (DELAY
      (ABSOLUTE
        (PORT I0  (1080:1080:1080) (1080:1080:1080))
        (IOPATH I0 O  (0:0:0) (0:0:0))
        (PORT I1  (1080:1080:1080) (1080:1080:1080))
        (IOPATH I1 O  (0:0:0) (0:0:0))
      )
    )
  )
  (CELL
    (CELLTYPE "X_AND2")
    (INSTANCE U41_N_1)
    (DELAY
      (ABSOLUTE
        (PORT I0  (0:0:0) (0:0:0))
        (IOPATH I0 O  (1600:1600:1600) (1600:1600:1600))
        (PORT I1  (1252:1252:1252) (1252:1252:1252))
        (IOPATH I1 O  (1600:1600:1600) (1600:1600:1600))
      )
    )
  )
  (CELL
    (CELLTYPE "X_INV")
    (INSTANCE U40_1I20_GTS_TRI_2_INV_2)
    (DELAY
      (ABSOLUTE
        (IOPATH I O  (0:0:0) (0:0:0))
      )
    )
  )
)