gate_clock.twr

实用的程序代码

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Xilinx TRACE, Version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Design file:              gate_clock.ncd
Physical constraint file: gate_clock.pcf
Device,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)
Report level:             summary report
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WARNING:bastw:172 - No timing constraints found, doing advanced analysis with
   offsets.

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Timing constraint: Default period analysis for net n_1
 2 items analyzed, 0 timing errors detected.
 Minimum period is   5.727ns.
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================================================================================
Timing constraint: Default OFFSET IN BEFORE analysis for clock "n_1"
 2 items analyzed, 0 timing errors detected.
 There is no minimum offset greater than zero for this constraint.
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================================================================================
Timing constraint: Default OFFSET OUT AFTER analysis for clock "n_1"
 1 item analyzed, 0 timing errors detected.
 Maximum allowable offset is  20.119ns.
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================================================================================
Timing constraint: Default path analysis
 4 items analyzed, 0 timing errors detected.
 Maximum delay is  11.597ns.
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All constraints were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 10 paths, 0 nets, and 10 connections (100.0% coverage)

Design statistics:
   Minimum period:   5.727ns (Maximum frequency: 174.611MHz)
   Maximum combinational path delay:  11.597ns
   Maximum output required time before clock:  20.119ns


Analysis completed Tue Jan  6 16:48:18 1998
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