map.mrp

实用的程序代码

             Xilinx Mapping Report File for Design "gate_clock2"
          Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Design Information
------------------
Command Line   : map gate_clock2.ngd -o map.ncd gate_clock2.pcf 
Target Device  : x4005e
Target Package : pc84
Target Speed   : -2
Mapper Version : xc4000e -- M1.4.12
Mapped Date    : Tue Jan  6 18:48:23 1998

Design Summary
--------------
   Number of errors:        0
   Number of warnings:      2
   Number of CLBs:              1 out of   196    1%
      CLB Flip Flops:       1
      4 input LUTs:         1
      3 input LUTs:         0
   Number of bonded IOBs:       6 out of    61    9%
      IOB Flops:            0
      IOB Latches:          0
   Number of global buffers:    1 out of     8   12%
   Number of secondary CLKs:    1 out of     4   25%
Total equivalent gate count for design: 12
Additional JTAG gate count for IOBs:    288

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Design Attributes
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - Added Logic
Section 7 - Expanded Logic
Section 8 - Signal Cross-Reference
Section 9 - Symbol Cross-Reference
Section 10 - IOB Properties
Section 11 - RPMs
Section 12 - Guide Report

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:baste:21 - Chipcheck: The signal "n83" is connected to the asynchronous
   set/reset of every flip-flop in the design.  Using the dedicated GSR/GR
   (global set/reset) pin on the STARTUP component will reduce the ammount of
   routing resources required to implement the design.  To use GSR/GR,
   disconnect the "n83" signal from the reset pin of every flip-flop in the
   design, and connect it to the GSR/GR pin of the STARTUP component.  Note that
   all flip-flops on the device will be cleared when GSR/GR goes active.
WARNING:baste:24 - All of the external outputs in this design are using
   slew-rate-limited output drivers.  The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the original
   design.  Please see your vendor interface documentation for specific
   information on how to do this within your design-entry tool.
   Note: You should be careful not to designate too many outputs which switch
   together as fast, because this can cause excessive ground bounce.  For more
   information on this subject, please refer to the IOB switching characteristic
   guidelines for the device you are using in the Programmable Logic Data Book.

Section 3 - Design Attributes
-----------------------------

Section 4 - Removed Logic Summary
---------------------------------
   1 block(s) removed
   1 block(s) optimized away
   1 signal(s) merged

Section 5 - Removed Logic
-------------------------
Block "U43" (INV) redundant - removed.
Block "n83.ZERO" (X_ZERO) removed due to optimization.

Merged Signal(s):
The signal "n84" was merged into signal "n_1".

Section 6 - Added Logic
-----------------------

Section 7 - Expanded Logic
--------------------------
To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE
and rerun MAP.

Section 8 - Signal Cross-Reference
----------------------------------
To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE
and rerun MAP.

Section 9 - Symbol Cross-Reference
----------------------------------
To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE
and rerun MAP.

Section 10 - IOB Properties
---------------------------
"OUT1" (IOB) : SLEW=SLOW

Section 11 - RPMs
-----------------

Section 12 - Guide Report
-------------------------
Guide not run on this design.