time_sim.v

实用的程序代码

// Xilinx Verilog produced by program ngd2ver, Version M1.4.12
// Date: Tue Jan  6 18:51:24 1998
// Design file: time_sim.nga
// Device: 4005epc84-2
`timescale 1 ns/1 ps
`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd

  module gate_clock (IN1, IN2, DATA, CLK, LOAD, OUT1);
    input IN1;
    input IN2;
    input DATA;
    input CLK;
    input LOAD;
    output OUT1;

    wire n55, n56, n57, n58, n59, n81, n_1, n79, n80, OUT1_reg_GSR_OR, 
    \U36/$1I20_GTS_TRI , \U31/clkio_bufsig , \U32/clkio_bufsig , 
    \U34/clkio_bufsig , \U37/2_0 , \U36/$1I20_GTS_TRI_2_INV , GND;
    `ifdef GSR_SIGNAL
      wire GSR = `GSR_SIGNAL ;
    `else
      wire GSR ;
    `endif
    `ifdef GTS_SIGNAL
      wire GTS = `GTS_SIGNAL ;
    `else
      wire GTS ;
    `endif
    initial $sdf_annotate("time_sim.sdf");

    X_BUF U33 (.IN (DATA), .OUT (n57));
    X_BUF U35 (.IN (LOAD), .OUT (n59));
    X_FF OUT1_reg (.IN (n57), .CLK (n80), .CE (n59), .SET (GND), .RST 
    (OUT1_reg_GSR_OR), .OUT (n81));
    X_INV U39 (.IN (n_1), .OUT (n80));
    X_IPAD IN1_PAD (.PAD (IN1));
    X_IPAD IN2_PAD (.PAD (IN2));
    X_IPAD DATA_PAD (.PAD (DATA));
    X_IPAD CLK_PAD (.PAD (CLK));
    X_IPAD LOAD_PAD (.PAD (LOAD));
    X_OPAD OUT1_PAD (.PAD (OUT1));
    X_ZERO n79_ZERO (.OUT (n79));
    X_OR2 OUT1_reg_GSR_OR_27 (.IN0 (n79), .IN1 (GSR), .OUT (OUT1_reg_GSR_OR));
    X_BUF \U36/$1I20  (.IN (n81), .OUT (\U36/$1I20_GTS_TRI ));
    X_TRI \U36/$1I20_GTS_TRI_28  (.IN (\U36/$1I20_GTS_TRI ), .OUT (OUT1), .CTL 
    (\U36/$1I20_GTS_TRI_2_INV ));
    X_CKBUF \U31/clkbuf  (.IN (\U31/clkio_bufsig ), .OUT (n55));
    X_BUF \U31/clkio_buf  (.IN (IN1), .OUT (\U31/clkio_bufsig ));
    X_CKBUF \U32/clkbuf  (.IN (\U32/clkio_bufsig ), .OUT (n56));
    X_BUF \U32/clkio_buf  (.IN (IN2), .OUT (\U32/clkio_bufsig ));
    X_CKBUF \U34/clkbuf  (.IN (\U34/clkio_bufsig ), .OUT (n58));
    X_BUF \U34/clkio_buf  (.IN (CLK), .OUT (\U34/clkio_bufsig ));
    X_AND2 \U37/n_1/2_0  (.IN0 (n55), .IN1 (n56), .OUT (\U37/2_0 ));
    X_AND2 \U37/n_1  (.IN0 (\U37/2_0 ), .IN1 (n58), .OUT (n_1));
    X_INV \U36/$1I20_GTS_TRI_2_INV_29  (.IN (GTS), .OUT 
    (\U36/$1I20_GTS_TRI_2_INV ));
    X_ZERO GND_30 (.OUT (GND));
    X_PD NGD2VER_PD_23 (.OUT (GSR) );
    X_PD NGD2VER_PD_24 (.OUT (GTS) );
  endmodule