dynamic_digital.tan.qmsg

来自「利用两个数码管」· QMSG 代码 · 共 12 行 · 第 1/2 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 6 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register countge\[3\] register countge\[2\] 75.19 MHz 13.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 75.19 MHz between source register \"countge\[3\]\" and destination register \"countge\[2\]\" (period= 13.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.800 ns + Longest register register " "Info: + Longest register to register delay is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns countge\[3\] 1 REG LC27 57 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC27; Fanout = 57; REG Node = 'countge\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countge[3] } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.300 ns) 4.300 ns countge\[2\]~639 2 COMB LC28 1 " "Info: 2: + IC(3.000 ns) + CELL(1.300 ns) = 4.300 ns; Loc. = LC28; Fanout = 1; COMB Node = 'countge\[2\]~639'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.300 ns" { countge[3] countge[2]~639 } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 5.200 ns countge\[2\]~633 3 COMB LC29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.900 ns) = 5.200 ns; Loc. = LC29; Fanout = 1; COMB Node = 'countge\[2\]~633'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { countge[2]~639 countge[2]~633 } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 6.100 ns countge\[2\]~614 4 COMB LC30 1 " "Info: 4: + IC(0.000 ns) + CELL(0.900 ns) = 6.100 ns; Loc. = LC30; Fanout = 1; COMB Node = 'countge\[2\]~614'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { countge[2]~633 countge[2]~614 } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.700 ns) 8.800 ns countge\[2\] 5 REG LC31 42 " "Info: 5: + IC(0.000 ns) + CELL(2.700 ns) = 8.800 ns; Loc. = LC31; Fanout = 42; REG Node = 'countge\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { countge[2]~614 countge[2] } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns ( 65.91 % ) " "Info: Total cell delay = 5.800 ns ( 65.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 34.09 % ) " "Info: Total interconnect delay = 3.000 ns ( 34.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.800 ns" { countge[3] countge[2]~639 countge[2]~633 countge[2]~614 countge[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.800 ns" { countge[3] countge[2]~639 countge[2]~633 countge[2]~614 countge[2] } { 0.000ns 3.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 0.900ns 2.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC48 22 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC48; Fanout = 22; REG Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 10.200 ns countge\[2\] 3 REG LC31 42 " "Info: 3: + IC(3.000 ns) + CELL(2.200 ns) = 10.200 ns; Loc. = LC31; Fanout = 42; REG Node = 'countge\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { clk1 countge[2] } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 70.59 % ) " "Info: Total cell delay = 7.200 ns ( 70.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 29.41 % ) " "Info: Total interconnect delay = 3.000 ns ( 29.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.200 ns" { clk clk1 countge[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.200 ns" { clk clk~out clk1 countge[2] } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.200 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC48 22 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC48; Fanout = 22; REG Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 10.200 ns countge\[3\] 3 REG LC27 57 " "Info: 3: + IC(3.000 ns) + CELL(2.200 ns) = 10.200 ns; Loc. = LC27; Fanout = 57; REG Node = 'countge\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { clk1 countge[3] } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 70.59 % ) " "Info: Total cell delay = 7.200 ns ( 70.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 29.41 % ) " "Info: Total interconnect delay = 3.000 ns ( 29.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.200 ns" { clk clk1 countge[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.200 ns" { clk clk~out clk1 countge[3] } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.200 ns" { clk clk1 countge[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.200 ns" { clk clk~out clk1 countge[2] } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.200 ns" { clk clk1 countge[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.200 ns" { clk clk~out clk1 countge[3] } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.800 ns" { countge[3] countge[2]~639 countge[2]~633 countge[2]~614 countge[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.800 ns" { countge[3] countge[2]~639 countge[2]~633 countge[2]~614 countge[2] } { 0.000ns 3.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.900ns 0.900ns 2.700ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.200 ns" { clk clk1 countge[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.200 ns" { clk clk~out clk1 countge[2] } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.200 ns" { clk clk1 countge[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.200 ns" { clk clk~out clk1 countge[3] } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk duan\[6\] countge\[0\] 24.600 ns register " "Info: tco from clock \"clk\" to destination pin \"duan\[6\]\" through register \"countge\[0\]\" is 24.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns clk1 2 REG LC48 22 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC48; Fanout = 22; REG Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1 } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 10.200 ns countge\[0\] 3 REG LC24 42 " "Info: 3: + IC(3.000 ns) + CELL(2.200 ns) = 10.200 ns; Loc. = LC24; Fanout = 42; REG Node = 'countge\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { clk1 countge[0] } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 70.59 % ) " "Info: Total cell delay = 7.200 ns ( 70.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 29.41 % ) " "Info: Total interconnect delay = 3.000 ns ( 29.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.200 ns" { clk clk1 countge[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.200 ns" { clk clk~out clk1 countge[0] } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.800 ns + Longest register pin " "Info: + Longest register to pin delay is 12.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns countge\[0\] 1 REG LC24 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC24; Fanout = 42; REG Node = 'countge\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { countge[0] } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.800 ns) 6.800 ns Mux0~417 2 COMB SEXP10 5 " "Info: 2: + IC(3.000 ns) + CELL(3.800 ns) = 6.800 ns; Loc. = SEXP10; Fanout = 5; COMB Node = 'Mux0~417'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.800 ns" { countge[0] Mux0~417 } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 11.200 ns Mux0~425 3 COMB LC6 1 " "Info: 3: + IC(0.000 ns) + CELL(4.400 ns) = 11.200 ns; Loc. = LC6; Fanout = 1; COMB Node = 'Mux0~425'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { Mux0~417 Mux0~425 } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 12.800 ns duan\[6\] 4 PIN PIN_99 0 " "Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 12.800 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'duan\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { Mux0~425 duan[6] } "NODE_NAME" } } { "Dynamic_digital.vhd" "" { Text "D:/CPLD开发板/2.epm3128板资料/1实验代码部分（vhdl在板子上可以直接运行）/7 数码管动态显示/Dynamic_digita/Dynamic_digital.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.800 ns ( 76.56 % ) " "Info: Total cell delay = 9.800 ns ( 76.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 23.44 % ) " "Info: Total interconnect delay = 3.000 ns ( 23.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.800 ns" { countge[0] Mux0~417 Mux0~425 duan[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.800 ns" { countge[0] Mux0~417 Mux0~425 duan[6] } { 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 3.800ns 4.400ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.200 ns" { clk clk1 countge[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.200 ns" { clk clk~out clk1 countge[0] } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.800 ns" { countge[0] Mux0~417 Mux0~425 duan[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.800 ns" { countge[0] Mux0~417 Mux0~425 duan[6] } { 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 3.800ns 4.400ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 12 10:56:20 2008 " "Info: Processing ended: Tue Aug 12 10:56:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}