color_char_mode_svga_ctrl.tlg

此ip核是xvga视频接口控制器

Selecting top level module COLOR_CHAR_MODE_SVGA_CTRL
Synthesizing module SVGA_TIMING_GENERATION
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\SVGA_TIMING_GENERATION.v":358:26:358:43|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\SVGA_TIMING_GENERATION.v":364:19:364:28|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\SVGA_TIMING_GENERATION.v":370:27:370:44|Removing redundant assignment
Synthesizing module RAMB16_S9
Synthesizing module CHAR_GEN_ROM
Synthesizing module CHARACTER_MODE
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":189:35:189:61|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":204:31:204:53|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":209:32:209:58|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":210:28:210:50|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":211:13:211:20|Removing redundant assignment
@W: CL159 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":63:14:63:25|Input char_address is unused
Synthesizing module COLOR_PIPE
Synthesizing module CLUT
@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <5> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <4> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <3> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <2> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <1> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <5> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <4> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <3> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <2> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <1> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <5> of blue_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <4> of blue_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <3> of blue_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <2> of blue_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <1> of blue_data[7:0] 

Synthesizing module COLOR_CHAR_MODE_SVGA_CTRL
@W: CS142 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\COLOR_CHAR_MODE_SVGA_CTRL.v":64:0:64:16|Range of port char_mode_address in port declaration and body are different.
@W: CL157 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\COLOR_CHAR_MODE_SVGA_CTRL.v":85:9:85:24|*Output char_read_enable has undriven bits - a simulation mismatch is possible