📄 color_char_mode_svga_ctrl.srr
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SVGA_TIMING_GENERATION.un1_line_count_6_cry_6 MUXCY_L LO Out 0.036 2.572 -
un1_line_count_6_cry_6 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_7 MUXCY_L CI In - 2.572 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_7 MUXCY_L LO Out 0.036 2.609 -
un1_line_count_6_cry_7 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_8 MUXCY_L CI In - 2.609 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_8 MUXCY_L LO Out 0.036 2.646 -
un1_line_count_6_cry_8 Net - - 0.000 - 1
SVGA_TIMING_GENERATION.un1_line_count_6_s_9 XORCY CI In - 2.646 -
SVGA_TIMING_GENERATION.un1_line_count_6_s_9 XORCY O Out 0.692 3.337 -
un1_line_count_6_s_9_n Net - - 0.270 - 1
g0_3 LUT4_L I0 In - 3.607 -
g0_3 LUT4_L LO Out 0.264 3.871 -
SVGA_TIMING_GENERATION.N_84_i Net - - 0.095 - 1
SVGA_TIMING_GENERATION.line_count[9] FDC D In - 3.966 -
===============================================================================================================
Total path delay (propagation time + setup) of 4.174 is 2.797(67.0%) logic and 1.377(33.0%) route.
Path information for path number 2:
Requested Period: 3.362
- Setup time: 0.208
= Required time: 3.154
- Propagation time: 3.933
= Slack (non-critical) : -0.779
Number of logic level(s): 15
Starting point: SVGA_TIMING_GENERATION.line_count[1] / Q
Ending point: SVGA_TIMING_GENERATION.line_count[9] / D
The start point is clocked by COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock [rising] on pin C
The end point is clocked by COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------
SVGA_TIMING_GENERATION.line_count[1] FDC Q Out 0.370 0.370 -
line_count[1] Net - - 0.527 - 8
SVGA_TIMING_GENERATION.N_68_i_sx_L3_0 LUT4_L I0 In - 0.897 -
SVGA_TIMING_GENERATION.N_68_i_sx_L3_0 LUT4_L LO Out 0.264 1.161 -
N_68_i_sx_L3_0_n Net - - 0.095 - 1
SVGA_TIMING_GENERATION.N_68_i_sx LUT4 I1 In - 1.255 -
SVGA_TIMING_GENERATION.N_68_i_sx LUT4 O Out 0.264 1.519 -
N_68_i_sx Net - - 0.095 - 1
SVGA_TIMING_GENERATION.N_68_i LUT4 I1 In - 1.614 -
SVGA_TIMING_GENERATION.N_68_i LUT4 O Out 0.264 1.878 -
N_68_i Net - - 0.000 - 1
SVGA_TIMING_GENERATION.N_68_i_cy MUXCY_L S In - 1.878 -
SVGA_TIMING_GENERATION.N_68_i_cy MUXCY_L LO Out 0.407 2.285 -
N_68_i_cy Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_0 MUXCY_L CI In - 2.285 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_0 MUXCY_L LO Out 0.036 2.321 -
un1_line_count_6_cry_0 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_1 MUXCY_L CI In - 2.321 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_1 MUXCY_L LO Out 0.036 2.358 -
un1_line_count_6_cry_1 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_2 MUXCY_L CI In - 2.358 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_2 MUXCY_L LO Out 0.036 2.394 -
un1_line_count_6_cry_2 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_3 MUXCY_L CI In - 2.394 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_3 MUXCY_L LO Out 0.036 2.431 -
un1_line_count_6_cry_3 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_4 MUXCY_L CI In - 2.431 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_4 MUXCY_L LO Out 0.036 2.467 -
un1_line_count_6_cry_4 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_5 MUXCY_L CI In - 2.467 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_5 MUXCY_L LO Out 0.036 2.504 -
un1_line_count_6_cry_5 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_6 MUXCY_L CI In - 2.504 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_6 MUXCY_L LO Out 0.036 2.540 -
un1_line_count_6_cry_6 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_7 MUXCY_L CI In - 2.540 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_7 MUXCY_L LO Out 0.036 2.577 -
un1_line_count_6_cry_7 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_8 MUXCY_L CI In - 2.577 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_8 MUXCY_L LO Out 0.036 2.613 -
un1_line_count_6_cry_8 Net - - 0.000 - 1
SVGA_TIMING_GENERATION.un1_line_count_6_s_9 XORCY CI In - 2.613 -
SVGA_TIMING_GENERATION.un1_line_count_6_s_9 XORCY O Out 0.692 3.305 -
un1_line_count_6_s_9_n Net - - 0.270 - 1
g0_3 LUT4_L I0 In - 3.575 -
g0_3 LUT4_L LO Out 0.264 3.839 -
SVGA_TIMING_GENERATION.N_84_i Net - - 0.095 - 1
SVGA_TIMING_GENERATION.line_count[9] FDC D In - 3.933 -
===============================================================================================================
Total path delay (propagation time + setup) of 4.141 is 3.061(73.9%) logic and 1.080(26.1%) route.
Path information for path number 3:
Requested Period: 3.362
- Setup time: 0.208
= Required time: 3.154
- Propagation time: 3.898
= Slack (non-critical) : -0.744
Number of logic level(s): 15
Starting point: SVGA_TIMING_GENERATION.line_count[4] / Q
Ending point: SVGA_TIMING_GENERATION.line_count[9] / D
The start point is clocked by COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock [rising] on pin C
The end point is clocked by COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------
SVGA_TIMING_GENERATION.line_count[4] FDC Q Out 0.370 0.370 -
line_count[4] Net - - 0.492 - 5
SVGA_TIMING_GENERATION.N_68_i_sx_L1_0 LUT4 I0 In - 0.862 -
SVGA_TIMING_GENERATION.N_68_i_sx_L1_0 LUT4 O Out 0.264 1.126 -
N_68_i_sx_L1_0_n Net - - 0.095 - 1
SVGA_TIMING_GENERATION.N_68_i_sx LUT4 I0 In - 1.220 -
SVGA_TIMING_GENERATION.N_68_i_sx LUT4 O Out 0.264 1.484 -
N_68_i_sx Net - - 0.095 - 1
SVGA_TIMING_GENERATION.N_68_i LUT4 I1 In - 1.579 -
SVGA_TIMING_GENERATION.N_68_i LUT4 O Out 0.264 1.843 -
N_68_i Net - - 0.000 - 1
SVGA_TIMING_GENERATION.N_68_i_cy MUXCY_L S In - 1.843 -
SVGA_TIMING_GENERATION.N_68_i_cy MUXCY_L LO Out 0.407 2.250 -
N_68_i_cy Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_0 MUXCY_L CI In - 2.250 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_0 MUXCY_L LO Out 0.036 2.286 -
un1_line_count_6_cry_0 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_1 MUXCY_L CI In - 2.286 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_1 MUXCY_L LO Out 0.036 2.323 -
un1_line_count_6_cry_1 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_2 MUXCY_L CI In - 2.323 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_2 MUXCY_L LO Out 0.036 2.359 -
un1_line_count_6_cry_2 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_3 MUXCY_L CI In - 2.359 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_3 MUXCY_L LO Out 0.036 2.396 -
un1_line_count_6_cry_3 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_4 MUXCY_L CI In - 2.396 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_4 MUXCY_L LO Out 0.036 2.432 -
un1_line_count_6_cry_4 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_5 MUXCY_L CI In - 2.432 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_5 MUXCY_L LO Out 0.036 2.469 -
un1_line_count_6_cry_5 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_6 MUXCY_L CI In - 2.469 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_6 MUXCY_L LO Out 0.036 2.505 -
un1_line_count_6_cry_6 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_7 MUXCY_L CI In - 2.505 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_7 MUXCY_L LO Out 0.036 2.542 -
un1_line_count_6_cry_7 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_8 MUXCY_L CI In - 2.542 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_8 MUXCY_L LO Out 0.036 2.578 -
un1_line_count_6_cry_8 Net - - 0.000 - 1
SVGA_TIMING_GENERATION.un1_line_count_6_s_9 XORCY CI In - 2.578 -
SVGA_TIMING_GENERATION.un1_line_count_6_s_9 XORCY O Out 0.692 3.270 -
un1_line_count_6_s_9_n Net - - 0.270 - 1
g0_3 LUT4_L I0 In - 3.540 -
g0_3 LUT4_L LO Out 0.264 3.804 -
SVGA_TIMING_GENERATION.N_84_i Net - - 0.095 - 1
SVGA_TIMING_GENERATION.line_count[9] FDC D In - 3.898 -
===============================================================================================================
Total path delay (propagation time + setup) of 4.106 is 3.061(74.5%) logic and 1.045(25.5%) route.
Path information for path number 4:
Requested Period: 3.362
- Setup time: 0.208
= Required time: 3.154
- Propagation time: 3.898
= Slack (non-critical) : -0.744
Number of logic level(s): 15
Starting point: SVGA_TIMING_GENERATION.line_count[6] / Q
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