📄 color_char_mode_svga_ctrl.srr
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Timing driven replication report
No replication required.
5 0h:0m:2s -1.10ns 195 / 140
6 0h:0m:2s -1.10ns 195 / 140
------------------------------------------------------------
Net buffering Report for view:work.COLOR_CHAR_MODE_SVGA_CTRL(verilog):
No nets needed buffering.
@N: FX164 |The option to pack flops in the IOB has not been specified
Writing Analyst data base C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\rev_1\COLOR_CHAR_MODE_SVGA_CTRL.srm
Writing EDIF Netlist and constraint files
Found clock COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock with period 3.36ns
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Feb 22 10:50:18 2005
#
Top view: COLOR_CHAR_MODE_SVGA_CTRL
Requested Frequency: 297.4 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: -0.812
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------------------------------------
COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock 297.4 MHz 239.6 MHz 3.362 4.173 -0.812 inferred Autoconstr_clkgroup_0
===============================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock | 3.362 -0.812 | No paths - | No paths - | No paths -
=====================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------------------------
SVGA_TIMING_GENERATION.pixel_count_fast[0] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q pixel_count_fast[0] 0.370 -0.812
SVGA_TIMING_GENERATION.line_count[1] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q line_count[1] 0.370 -0.779
SVGA_TIMING_GENERATION.line_count[4] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q line_count[4] 0.370 -0.744
SVGA_TIMING_GENERATION.line_count[6] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q line_count[6] 0.370 -0.744
SVGA_TIMING_GENERATION.line_count[8] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q line_count[8] 0.370 -0.744
SVGA_TIMING_GENERATION.line_count[9] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q line_count[9] 0.370 -0.744
SVGA_TIMING_GENERATION.pixel_count_fast[2] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q pixel_count_fast[2] 0.370 -0.731
SVGA_TIMING_GENERATION.line_count_fast[2] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q line_count_fast[2] 0.370 -0.701
SVGA_TIMING_GENERATION.line_count_fast[7] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q line_count_fast[7] 0.370 -0.701
SVGA_TIMING_GENERATION.pixel_count_fast[9] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC Q pixel_count_fast[9] 0.370 -0.701
====================================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------------------------------
SVGA_TIMING_GENERATION.line_count[9] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D N_84_i 3.154 -0.812
SVGA_TIMING_GENERATION.line_count[7] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D un1_line_count_6_s_7_n 3.154 -0.421
SVGA_TIMING_GENERATION.line_count_fast[7] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D un1_line_count_6_s_7_n 3.154 -0.421
SVGA_TIMING_GENERATION.line_count[6] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D N_82_i 3.362 -0.400
SVGA_TIMING_GENERATION.line_count[5] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D N_80_i 3.362 -0.363
SVGA_TIMING_GENERATION.char_count[16] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D char_count_s[16] 3.362 -0.332
SVGA_TIMING_GENERATION.line_count[4] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D N_78_i 3.362 -0.327
SVGA_TIMING_GENERATION.char_count[15] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D char_count_s[15] 3.362 -0.295
SVGA_TIMING_GENERATION.line_count[3] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D un1_line_count_6_s_3_n 3.154 -0.275
SVGA_TIMING_GENERATION.line_count_fast[3] COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock FDC D un1_line_count_6_s_3_n 3.154 -0.275
=======================================================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 3.362
- Setup time: 0.208
= Required time: 3.154
- Propagation time: 3.966
= Slack (critical) : -0.812
Number of logic level(s): 14
Starting point: SVGA_TIMING_GENERATION.pixel_count_fast[0] / Q
Ending point: SVGA_TIMING_GENERATION.line_count[9] / D
The start point is clocked by COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock [rising] on pin C
The end point is clocked by COLOR_CHAR_MODE_SVGA_CTRL|pixel_clock [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------------
SVGA_TIMING_GENERATION.pixel_count_fast[0] FDC Q Out 0.370 0.370 -
pixel_count_fast[0] Net - - 0.448 - 2
SVGA_TIMING_GENERATION.line_count15_i_o2 LUT2 I0 In - 0.818 -
SVGA_TIMING_GENERATION.line_count15_i_o2 LUT2 O Out 0.264 1.082 -
N_123 Net - - 0.564 - 12
SVGA_TIMING_GENERATION.N_68_i LUT4 I2 In - 1.646 -
SVGA_TIMING_GENERATION.N_68_i LUT4 O Out 0.264 1.910 -
N_68_i Net - - 0.000 - 1
SVGA_TIMING_GENERATION.N_68_i_cy MUXCY_L S In - 1.910 -
SVGA_TIMING_GENERATION.N_68_i_cy MUXCY_L LO Out 0.407 2.317 -
N_68_i_cy Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_0 MUXCY_L CI In - 2.317 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_0 MUXCY_L LO Out 0.036 2.353 -
un1_line_count_6_cry_0 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_1 MUXCY_L CI In - 2.353 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_1 MUXCY_L LO Out 0.036 2.390 -
un1_line_count_6_cry_1 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_2 MUXCY_L CI In - 2.390 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_2 MUXCY_L LO Out 0.036 2.426 -
un1_line_count_6_cry_2 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_3 MUXCY_L CI In - 2.426 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_3 MUXCY_L LO Out 0.036 2.463 -
un1_line_count_6_cry_3 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_4 MUXCY_L CI In - 2.463 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_4 MUXCY_L LO Out 0.036 2.499 -
un1_line_count_6_cry_4 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_5 MUXCY_L CI In - 2.499 -
SVGA_TIMING_GENERATION.un1_line_count_6_cry_5 MUXCY_L LO Out 0.036 2.536 -
un1_line_count_6_cry_5 Net - - 0.000 - 2
SVGA_TIMING_GENERATION.un1_line_count_6_cry_6 MUXCY_L CI In - 2.536 -
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