color_char_mode_svga_ctrl.srr

此ip核是xvga视频接口控制器

$ Start of Compile
#Tue Feb 22 10:50:15 2005

Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_defines.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLOCKGEN.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHAR_RAM.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\COLOR_PIPE.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\DRIVE_DAC_DATA.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\SVGA_TIMING_GENERATION.v"
@I:"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\SVGA_TIMING_GENERATION.v":"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_defines.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHAR_GEN_ROM.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\COLOR_RAM.v"
@I::"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\COLOR_CHAR_MODE_SVGA_CTRL.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module COLOR_CHAR_MODE_SVGA_CTRL
Synthesizing module SVGA_TIMING_GENERATION
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\SVGA_TIMING_GENERATION.v":358:26:358:43|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\SVGA_TIMING_GENERATION.v":364:19:364:28|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\SVGA_TIMING_GENERATION.v":370:27:370:44|Removing redundant assignment
Synthesizing module RAMB16_S9
Synthesizing module CHAR_GEN_ROM
Synthesizing module CHARACTER_MODE
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":189:35:189:61|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":204:31:204:53|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":209:32:209:58|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":210:28:210:50|Removing redundant assignment
@N: CG179 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":211:13:211:20|Removing redundant assignment
@W: CL159 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CHARACTER_MODE.v":63:14:63:25|Input char_address is unused
Synthesizing module COLOR_PIPE
Synthesizing module CLUT
@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <5> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <4> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <3> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <2> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <1> of red_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <5> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <4> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <3> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <2> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <1> of green_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <5> of blue_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <4> of blue_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <3> of blue_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <2> of blue_data[7:0] 

@W: CL171 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\CLUT.v":197:0:197:5|Pruning Register bit <1> of blue_data[7:0] 

Synthesizing module COLOR_CHAR_MODE_SVGA_CTRL
@W: CS142 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\COLOR_CHAR_MODE_SVGA_CTRL.v":64:0:64:16|Range of port char_mode_address in port declaration and body are different.
@W: CL157 :"C:\ML_XUP\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\COLOR_CHAR_MODE_SVGA_CTRL.v":85:9:85:24|*Output char_read_enable has undriven bits - a simulation mismatch is possible 
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Xilinx Technology Mapper, version 7.3.5, Build 256R, built Mar 25 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved


@W: MO111 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":85:9:85:24|tristate driver char_read_enable on net char_read_enable has its enable tied to GND (module COLOR_CHAR_MODE_SVGA_CTRL) 
Automatic dissolve at startup in view:work.CHARACTER_MODE(verilog) of CHAR_GEN_ROM(CHAR_GEN_ROM)
Automatic dissolve at startup in view:work.COLOR_CHAR_MODE_SVGA_CTRL(verilog) of COLOR_PIPE(COLOR_PIPE)
@N:"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":344:0:344:5|Found counter in view:work.SVGA_TIMING_GENERATION(verilog) inst char_count[16:0]
@N: FA190 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":153:17:153:30|Found addmux in view:work.SVGA_TIMING_GENERATION(verilog) inst un1_line_count_6[9:0]  
Automatic dissolve during optimization of view:work.COLOR_CHAR_MODE_SVGA_CTRL(verilog) of CLUT(CLUT)
Automatic dissolve during optimization of view:work.COLOR_CHAR_MODE_SVGA_CTRL(verilog) of CHARACTER_MODE(CHARACTER_MODE)
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_RED[1],  because it is equivalent to instance VGA_OUT_RED[2]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_RED[0],  because it is equivalent to instance VGA_OUT_RED[2]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_RED[5],  because it is equivalent to instance VGA_OUT_RED[2]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_RED[4],  because it is equivalent to instance VGA_OUT_RED[2]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_RED[3],  because it is equivalent to instance VGA_OUT_RED[2]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_GREEN[3],  because it is equivalent to instance VGA_OUT_GREEN[4]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_GREEN[2],  because it is equivalent to instance VGA_OUT_GREEN[4]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_GREEN[1],  because it is equivalent to instance VGA_OUT_GREEN[4]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_GREEN[0],  because it is equivalent to instance VGA_OUT_GREEN[4]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_GREEN[5],  because it is equivalent to instance VGA_OUT_GREEN[4]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_BLUE[4],  because it is equivalent to instance VGA_OUT_BLUE[5]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_BLUE[3],  because it is equivalent to instance VGA_OUT_BLUE[5]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_BLUE[2],  because it is equivalent to instance VGA_OUT_BLUE[5]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_BLUE[1],  because it is equivalent to instance VGA_OUT_BLUE[5]
@W: BN132 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v":165:0:165:5|Removing instance VGA_OUT_BLUE[0],  because it is equivalent to instance VGA_OUT_BLUE[5]
@N: MT204 |Autoconstrain Mode is ON
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:1s		    -1.96ns		 170 /       126
   2		0h:0m:1s		    -1.44ns		 170 /       126
   3		0h:0m:1s		    -1.44ns		 170 /       126
   4		0h:0m:1s		    -1.44ns		 170 /       126
------------------------------------------------------------

Timing driven replication report
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":104:0:104:5|Instance "SVGA_TIMING_GENERATION.pixel_count[8]" with 6 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":104:0:104:5|Instance "SVGA_TIMING_GENERATION.pixel_count[9]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":104:0:104:5|Instance "SVGA_TIMING_GENERATION.pixel_count[3]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":104:0:104:5|Instance "SVGA_TIMING_GENERATION.pixel_count[4]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":104:0:104:5|Instance "SVGA_TIMING_GENERATION.pixel_count[10]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":140:0:140:5|Instance "SVGA_TIMING_GENERATION.line_count[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":140:0:140:5|Instance "SVGA_TIMING_GENERATION.line_count[2]" with 9 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":398:0:398:5|Instance "SVGA_TIMING_GENERATION.reset_char_count" with 36 loads has been replicated 3 time(s) to improve timing 
Added 10 Registers via timing driven replication
Added 0 LUTs via timing driven replication

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":417:0:417:5|Instance "SVGA_TIMING_GENERATION.hold_char_count" with 19 loads has been replicated 1 time(s) to improve timing 
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication

Timing driven replication report
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":104:0:104:5|Instance "SVGA_TIMING_GENERATION.pixel_count[0]" with 8 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":104:0:104:5|Instance "SVGA_TIMING_GENERATION.pixel_count[2]" with 8 loads has been replicated 1 time(s) to improve timing 
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":104:0:104:5|Instance "SVGA_TIMING_GENERATION.N_72_i" with 2 loads has been replicated 1 time(s) to improve timing 
Added 2 Registers via timing driven replication
Added 1 LUTs via timing driven replication

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:1s		    -1.22ns		 185 /       139
   2		0h:0m:1s		    -1.22ns		 184 /       139
   3		0h:0m:1s		    -1.22ns		 184 /       139
   4		0h:0m:1s		    -1.22ns		 184 /       139
Timing driven replication report
No replication required.

   5		0h:0m:1s		    -1.22ns		 184 /       139
   6		0h:0m:1s		    -1.31ns		 186 /       139
   7		0h:0m:1s		    -1.31ns		 186 /       139
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
@N: FX235 :"c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v":140:0:140:5|Instance "SVGA_TIMING_GENERATION.line_count[3]" with 6 loads has been replicated 1 time(s) to improve timing 
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:0m:1s		    -1.10ns		 195 /       140
   2		0h:0m:2s		    -1.10ns		 195 /       140
   3		0h:0m:2s		    -1.10ns		 195 /       140
   4		0h:0m:2s		    -1.10ns		 195 /       140