color_char_mode_svga_ctrl.srd

此ip核是xvga视频接口控制器

f "noname"; #file 0
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_defines.v"; #file 1
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\clockgen.v"; #file 2
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\clut.v"; #file 3
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\char_ram.v"; #file 4
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\character_mode.v"; #file 5
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_pipe.v"; #file 6
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\drive_dac_data.v"; #file 7
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\svga_timing_generation.v"; #file 8
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\char_gen_rom.v"; #file 9
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_ram.v"; #file 10
f "c:\ml_xup\edk_6_3_builds\audio_filter\pcores\vga_controller_v1_00_a\hdl\verilog\color_char_mode_svga_ctrl.v"; #file 11
VNAME 'work.SVGA_TIMING_GENERATION.verilog'; # view id 0
VNAME 'work.CHARACTER_MODE.verilog'; # view id 1
VNAME 'work.COLOR_CHAR_MODE_SVGA_CTRL.verilog'; # view id 2
VNAME 'work.CHAR_GEN_ROM.verilog'; # view id 3
VNAME 'work.COLOR_PIPE.verilog'; # view id 4
VNAME 'work.CLUT.verilog'; # view id 5
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