spi_to_i2c.map.qmsg

VHDL实现SPI接口转I2c接口的源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 10:36:39 2007 " "Info: Processing started: Mon Nov 05 10:36:39 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SPI_to_I2C -c SPI_to_I2C " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SPI_to_I2C -c SPI_to_I2C" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SPI_to_I2C.v(204) " "Warning (10268): Verilog HDL information at SPI_to_I2C.v(204): Always Construct contains both blocking and non-blocking assignments" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 204 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SPI_to_I2C.v(235) " "Warning (10268): Verilog HDL information at SPI_to_I2C.v(235): Always Construct contains both blocking and non-blocking assignments" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 235 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SPI_to_I2C.v(263) " "Warning (10268): Verilog HDL information at SPI_to_I2C.v(263): Always Construct contains both blocking and non-blocking assignments" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 263 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SPI_to_I2C.v(286) " "Warning (10268): Verilog HDL information at SPI_to_I2C.v(286): Always Construct contains both blocking and non-blocking assignments" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 286 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../code/SPI_to_I2C.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file ../code/SPI_to_I2C.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPI_to_I2C " "Info: Found entity 1: SPI_to_I2C" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 SPI_slave " "Info: Found entity 2: SPI_slave" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 I2C_master " "Info: Found entity 3: I2C_master" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 123 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 internal_oss_altufm_osc_7p3 " "Info: Found entity 4: internal_oss_altufm_osc_7p3" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 314 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 divider " "Info: Found entity 5: divider" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 367 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SPI_to_I2C " "Info: Elaborating entity \"SPI_to_I2C\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "internal_oss_altufm_osc_7p3 internal_oss_altufm_osc_7p3:ufmosc " "Info: Elaborating entity \"internal_oss_altufm_osc_7p3\" for hierarchy \"internal_oss_altufm_osc_7p3:ufmosc\"" {  } { { "../code/SPI_to_I2C.v" "ufmosc" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 24 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divider divider:divide " "Info: Elaborating entity \"divider\" for hierarchy \"divider:divide\"" {  } { { "../code/SPI_to_I2C.v" "divide" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 26 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 SPI_to_I2C.v(382) " "Warning (10230): Verilog HDL assignment warning at SPI_to_I2C.v(382): truncated value with size 32 to match size of target (10)" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 382 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SPI_slave SPI_slave:spi " "Info: Elaborating entity \"SPI_slave\" for hierarchy \"SPI_slave:spi\"" {  } { { "../code/SPI_to_I2C.v" "spi" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 28 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_master I2C_master:i2c " "Info: Elaborating entity \"I2C_master\" for hierarchy \"I2C_master:i2c\"" {  } { { "../code/SPI_to_I2C.v" "i2c" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 30 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "status_reg\[7\] SPI_to_I2C.v(131) " "Warning (10034): Output port \"status_reg\[7\]\" at SPI_to_I2C.v(131) has no driver" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 131 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "status_reg\[6\] SPI_to_I2C.v(131) " "Warning (10034): Output port \"status_reg\[6\]\" at SPI_to_I2C.v(131) has no driver" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 131 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "status_reg\[5\] SPI_to_I2C.v(131) " "Warning (10034): Output port \"status_reg\[5\]\" at SPI_to_I2C.v(131) has no driver" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 131 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "status_reg\[4\] SPI_to_I2C.v(131) " "Warning (10034): Output port \"status_reg\[4\]\" at SPI_to_I2C.v(131) has no driver" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 131 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "status_reg\[3\] SPI_to_I2C.v(131) " "Warning (10034): Output port \"status_reg\[3\]\" at SPI_to_I2C.v(131) has no driver" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 131 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "status_reg\[2\] SPI_to_I2C.v(131) " "Warning (10034): Output port \"status_reg\[2\]\" at SPI_to_I2C.v(131) has no driver" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 131 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "status_reg\[1\] SPI_to_I2C.v(131) " "Warning (10034): Output port \"status_reg\[1\]\" at SPI_to_I2C.v(131) has no driver" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 131 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "I2C_master:i2c\|scl_out~reg0 data_in GND " "Warning (14130): Reduced register \"I2C_master:i2c\|scl_out~reg0\" with stuck data_in port to stuck value GND" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "120 " "Info: Implemented 120 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "2 " "Info: Implemented 2 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "113 " "Info: Implemented 113 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Info: Implemented 1 User Flash Memory blocks" {  } {  } 0 0 "Implemented %1!d! User Flash Memory blocks" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/quartus/SPI_to_I2C.map.smsg " "Info: Generated suppressed messages file U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/quartus/SPI_to_I2C.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 10:36:45 2007 " "Info: Processing ended: Mon Nov 05 10:36:45 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}