spi_to_i2c.fit.qmsg

VHDL实现SPI接口转I2c接口的源代码

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.810 ns register register " "Info: Estimated most critical path is register to register delay of 6.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_master:i2c\|count\[1\] 1 REG LAB_X6_Y3 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y3; Fanout = 16; REG Node = 'I2C_master:i2c\|count\[1\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_master:i2c|count[1] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 218 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.433 ns) + CELL(0.462 ns) 1.895 ns I2C_master:i2c\|sda_out~445 2 COMB LAB_X3_Y2 2 " "Info: 2: + IC(1.433 ns) + CELL(0.462 ns) = 1.895 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'I2C_master:i2c\|sda_out~445'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.895 ns" { I2C_master:i2c|count[1] I2C_master:i2c|sda_out~445 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.418 ns) + CELL(0.319 ns) 2.632 ns I2C_master:i2c\|sda_out~446 3 COMB LAB_X3_Y2 1 " "Info: 3: + IC(0.418 ns) + CELL(0.319 ns) = 2.632 ns; Loc. = LAB_X3_Y2; Fanout = 1; COMB Node = 'I2C_master:i2c\|sda_out~446'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.737 ns" { I2C_master:i2c|sda_out~445 I2C_master:i2c|sda_out~446 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(0.125 ns) 3.369 ns I2C_master:i2c\|sda_out~447 4 COMB LAB_X3_Y2 1 " "Info: 4: + IC(0.612 ns) + CELL(0.125 ns) = 3.369 ns; Loc. = LAB_X3_Y2; Fanout = 1; COMB Node = 'I2C_master:i2c\|sda_out~447'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.737 ns" { I2C_master:i2c|sda_out~446 I2C_master:i2c|sda_out~447 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.465 ns) + CELL(0.319 ns) 5.153 ns I2C_master:i2c\|sda_out~451 5 COMB LAB_X5_Y1 1 " "Info: 5: + IC(1.465 ns) + CELL(0.319 ns) = 5.153 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'I2C_master:i2c\|sda_out~451'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.784 ns" { I2C_master:i2c|sda_out~447 I2C_master:i2c|sda_out~451 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(0.125 ns) 5.890 ns I2C_master:i2c\|sda_out~452 6 COMB LAB_X5_Y1 1 " "Info: 6: + IC(0.612 ns) + CELL(0.125 ns) = 5.890 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'I2C_master:i2c\|sda_out~452'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.737 ns" { I2C_master:i2c|sda_out~451 I2C_master:i2c|sda_out~452 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.418 ns) + CELL(0.502 ns) 6.810 ns I2C_master:i2c\|sda_out 7 REG LAB_X5_Y1 1 " "Info: 7: + IC(0.418 ns) + CELL(0.502 ns) = 6.810 ns; Loc. = LAB_X5_Y1; Fanout = 1; REG Node = 'I2C_master:i2c\|sda_out'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.920 ns" { I2C_master:i2c|sda_out~452 I2C_master:i2c|sda_out } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.852 ns ( 27.20 % ) " "Info: Total cell delay = 1.852 ns ( 27.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.958 ns ( 72.80 % ) " "Info: Total interconnect delay = 4.958 ns ( 72.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.810 ns" { I2C_master:i2c|count[1] I2C_master:i2c|sda_out~445 I2C_master:i2c|sda_out~446 I2C_master:i2c|sda_out~447 I2C_master:i2c|sda_out~451 I2C_master:i2c|sda_out~452 I2C_master:i2c|sda_out } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "8 " "Info: Average interconnect usage is 8% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "8 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 8% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "I2C_master:i2c\|sda_out_en~1 (inverted) " "Info: Following pins have the same output enable: I2C_master:i2c\|sda_out_en~1 (inverted)" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional I2C_sda 2.5 V " "Info: Type bidirectional pin I2C_sda uses the 2.5 V I/O standard" {  } { { "v:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "v:/altera/72/quartus/bin/pin_planner.ppl" { I2C_sda } } } { "v:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "v:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_sda" } } } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 9 -1 0 } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_sda } "NODE_NAME" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_sda } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "I2C_master:i2c\|scl_out~en " "Info: Following pins have the same output enable: I2C_master:i2c\|scl_out~en" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional I2C_scl 2.5 V " "Info: Type bidirectional pin I2C_scl uses the 2.5 V I/O standard" {  } { { "v:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "v:/altera/72/quartus/bin/pin_planner.ppl" { I2C_scl } } } { "v:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "v:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_scl" } } } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 10 -1 0 } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_scl } "NODE_NAME" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_scl } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/quartus/SPI_to_I2C.fit.smsg " "Info: Generated suppressed messages file U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/quartus/SPI_to_I2C.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "173 " "Info: Allocated 173 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 10:36:54 2007 " "Info: Processing ended: Mon Nov 05 10:36:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}