spi_to_i2c.fit.qmsg

VHDL实现SPI接口转I2c接口的源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 10:36:47 2007 " "Info: Processing started: Mon Nov 05 10:36:47 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off SPI_to_I2C -c SPI_to_I2C " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SPI_to_I2C -c SPI_to_I2C" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "SPI_to_I2C EPM240GT100C3 " "Info: Selected device EPM240GT100C3 for design \"SPI_to_I2C\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570GT100C3 " "Info: Device EPM570GT100C3 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SPI_sclk Global clock " "Info: Automatically promoted signal \"SPI_sclk\" to use Global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 12 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "SPI_sclk " "Info: Pin \"SPI_sclk\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "v:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "v:/altera/72/quartus/bin/pin_planner.ppl" { SPI_sclk } } } { "v:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "v:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SPI_sclk" } } } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 12 -1 0 } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_sclk } "NODE_NAME" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_sclk } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "I2C_scl Global clock " "Info: Automatically promoted some destinations of signal \"I2C_scl\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "I2C_master:i2c\|sda_out1 " "Info: Destination \"I2C_master:i2c\|sda_out1\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "I2C_master:i2c\|scl_out~en " "Info: Destination \"I2C_master:i2c\|scl_out~en\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 156 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "I2C_master:i2c\|repeat_start_flag " "Info: Destination \"I2C_master:i2c\|repeat_start_flag\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 139 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "I2C_master:i2c\|start " "Info: Destination \"I2C_master:i2c\|start\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "I2C_master:i2c\|stop " "Info: Destination \"I2C_master:i2c\|stop\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 10 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "I2C_scl~0 " "Info: Pin \"I2C_scl~0\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "v:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "v:/altera/72/quartus/bin/pin_planner.ppl" { I2C_scl } } } { "v:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "v:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_scl" } } } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 10 -1 0 } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_scl } "NODE_NAME" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_scl } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "internal_oss_altufm_osc_7p3:ufmosc\|wire_maxii_ufm_block1_osc Global clock " "Info: Automatically promoted signal \"internal_oss_altufm_osc_7p3:ufmosc\|wire_maxii_ufm_block1_osc\" to use Global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 321 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "SPI_cs Global clock " "Info: Automatically promoted some destinations of signal \"SPI_cs\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "I2C_master:i2c\|sda_out1~317 " "Info: Destination \"I2C_master:i2c\|sda_out1~317\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 133 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SPI_slave:spi\|count_1\[1\] " "Info: Destination \"SPI_slave:spi\|count_1\[1\]\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 94 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SPI_slave:spi\|count_1\[0\] " "Info: Destination \"SPI_slave:spi\|count_1\[0\]\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 94 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SPI_slave:spi\|count_1\[2\] " "Info: Destination \"SPI_slave:spi\|count_1\[2\]\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 94 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SPI_slave:spi\|count_byte1 " "Info: Destination \"SPI_slave:spi\|count_byte1\" may be non-global or may not use global clock" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 45 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 13 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "SPI_cs " "Info: Pin \"SPI_cs\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "v:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "v:/altera/72/quartus/bin/pin_planner.ppl" { SPI_cs } } } { "v:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "v:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "SPI_cs" } } } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 13 -1 0 } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_cs } "NODE_NAME" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_cs } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}