spi_to_i2c.tan.qmsg

VHDL实现SPI接口转I2c接口的源代码

{ "Info" "ITDB_FULL_TCO_RESULT" "SPI_sclk SPI_miso SPI_slave:spi\|miso 7.268 ns register " "Info: tco from clock \"SPI_sclk\" to destination pin \"SPI_miso\" through register \"SPI_slave:spi\|miso\" is 7.268 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SPI_sclk source 4.126 ns + Longest register " "Info: + Longest clock path from clock \"SPI_sclk\" to source register is 4.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.047 ns) 1.047 ns SPI_sclk 1 CLK PIN_96 26 " "Info: 1: + IC(0.000 ns) + CELL(1.047 ns) = 1.047 ns; Loc. = PIN_96; Fanout = 26; CLK Node = 'SPI_sclk'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_sclk } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.505 ns) + CELL(0.574 ns) 4.126 ns SPI_slave:spi\|miso 2 REG LC_X4_Y2_N8 2 " "Info: 2: + IC(2.505 ns) + CELL(0.574 ns) = 4.126 ns; Loc. = LC_X4_Y2_N8; Fanout = 2; REG Node = 'SPI_slave:spi\|miso'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.079 ns" { SPI_sclk SPI_slave:spi|miso } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.621 ns ( 39.29 % ) " "Info: Total cell delay = 1.621 ns ( 39.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.505 ns ( 60.71 % ) " "Info: Total interconnect delay = 2.505 ns ( 60.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.126 ns" { SPI_sclk SPI_slave:spi|miso } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.126 ns" { SPI_sclk {} SPI_sclk~combout {} SPI_slave:spi|miso {} } { 0.000ns 0.000ns 2.505ns } { 0.000ns 1.047ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 41 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.907 ns + Longest register pin " "Info: + Longest register to pin delay is 2.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SPI_slave:spi\|miso 1 REG LC_X4_Y2_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y2_N8; Fanout = 2; REG Node = 'SPI_slave:spi\|miso'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_slave:spi|miso } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(1.636 ns) 2.907 ns SPI_miso 2 PIN PIN_91 0 " "Info: 2: + IC(1.271 ns) + CELL(1.636 ns) = 2.907 ns; Loc. = PIN_91; Fanout = 0; PIN Node = 'SPI_miso'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { SPI_slave:spi|miso SPI_miso } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 56.28 % ) " "Info: Total cell delay = 1.636 ns ( 56.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.271 ns ( 43.72 % ) " "Info: Total interconnect delay = 1.271 ns ( 43.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { SPI_slave:spi|miso SPI_miso } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.907 ns" { SPI_slave:spi|miso {} SPI_miso {} } { 0.000ns 1.271ns } { 0.000ns 1.636ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.126 ns" { SPI_sclk SPI_slave:spi|miso } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.126 ns" { SPI_sclk {} SPI_sclk~combout {} SPI_slave:spi|miso {} } { 0.000ns 0.000ns 2.505ns } { 0.000ns 1.047ns 0.574ns } "" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { SPI_slave:spi|miso SPI_miso } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.907 ns" { SPI_slave:spi|miso {} SPI_miso {} } { 0.000ns 1.271ns } { 0.000ns 1.636ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "SPI_slave:spi\|count_1\[2\] SPI_cs SPI_sclk 1.385 ns register " "Info: th for register \"SPI_slave:spi\|count_1\[2\]\" (data pin = \"SPI_cs\", clock pin = \"SPI_sclk\") is 1.385 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SPI_sclk destination 4.126 ns + Longest register " "Info: + Longest clock path from clock \"SPI_sclk\" to destination register is 4.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.047 ns) 1.047 ns SPI_sclk 1 CLK PIN_96 26 " "Info: 1: + IC(0.000 ns) + CELL(1.047 ns) = 1.047 ns; Loc. = PIN_96; Fanout = 26; CLK Node = 'SPI_sclk'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_sclk } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.505 ns) + CELL(0.574 ns) 4.126 ns SPI_slave:spi\|count_1\[2\] 2 REG LC_X3_Y3_N0 4 " "Info: 2: + IC(2.505 ns) + CELL(0.574 ns) = 4.126 ns; Loc. = LC_X3_Y3_N0; Fanout = 4; REG Node = 'SPI_slave:spi\|count_1\[2\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.079 ns" { SPI_sclk SPI_slave:spi|count_1[2] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.621 ns ( 39.29 % ) " "Info: Total cell delay = 1.621 ns ( 39.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.505 ns ( 60.71 % ) " "Info: Total interconnect delay = 2.505 ns ( 60.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.126 ns" { SPI_sclk SPI_slave:spi|count_1[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.126 ns" { SPI_sclk {} SPI_sclk~combout {} SPI_slave:spi|count_1[2] {} } { 0.000ns 0.000ns 2.505ns } { 0.000ns 1.047ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.138 ns + " "Info: + Micro hold delay of destination is 0.138 ns" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 94 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.879 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.731 ns) 0.731 ns SPI_cs 1 CLK PIN_95 19 " "Info: 1: + IC(0.000 ns) + CELL(0.731 ns) = 0.731 ns; Loc. = PIN_95; Fanout = 19; CLK Node = 'SPI_cs'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_cs } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.371 ns) + CELL(0.777 ns) 2.879 ns SPI_slave:spi\|count_1\[2\] 2 REG LC_X3_Y3_N0 4 " "Info: 2: + IC(1.371 ns) + CELL(0.777 ns) = 2.879 ns; Loc. = LC_X3_Y3_N0; Fanout = 4; REG Node = 'SPI_slave:spi\|count_1\[2\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.148 ns" { SPI_cs SPI_slave:spi|count_1[2] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.508 ns ( 52.38 % ) " "Info: Total cell delay = 1.508 ns ( 52.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.371 ns ( 47.62 % ) " "Info: Total interconnect delay = 1.371 ns ( 47.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.879 ns" { SPI_cs SPI_slave:spi|count_1[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.879 ns" { SPI_cs {} SPI_cs~combout {} SPI_slave:spi|count_1[2] {} } { 0.000ns 0.000ns 1.371ns } { 0.000ns 0.731ns 0.777ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.126 ns" { SPI_sclk SPI_slave:spi|count_1[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.126 ns" { SPI_sclk {} SPI_sclk~combout {} SPI_slave:spi|count_1[2] {} } { 0.000ns 0.000ns 2.505ns } { 0.000ns 1.047ns 0.574ns } "" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.879 ns" { SPI_cs SPI_slave:spi|count_1[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.879 ns" { SPI_cs {} SPI_cs~combout {} SPI_slave:spi|count_1[2] {} } { 0.000ns 0.000ns 1.371ns } { 0.000ns 0.731ns 0.777ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 10:37:04 2007 " "Info: Processing ended: Mon Nov 05 10:37:04 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}