spi_to_i2c.tan.qmsg

VHDL实现SPI接口转I2c接口的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "I2C_scl register I2C_master:i2c\|count\[2\] register I2C_master:i2c\|data_out\[2\] 105.93 MHz 9.44 ns Internal " "Info: Clock \"I2C_scl\" has Internal fmax of 105.93 MHz between source register \"I2C_master:i2c\|count\[2\]\" and destination register \"I2C_master:i2c\|data_out\[2\]\" (period= 9.44 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.277 ns + Longest register register " "Info: + Longest register to register delay is 4.277 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_master:i2c\|count\[2\] 1 REG LC_X6_Y3_N8 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y3_N8; Fanout = 13; REG Node = 'I2C_master:i2c\|count\[2\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_master:i2c|count[2] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 218 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.571 ns) 1.176 ns I2C_master:i2c\|Equal1~90 2 COMB LC_X6_Y3_N0 3 " "Info: 2: + IC(0.605 ns) + CELL(0.571 ns) = 1.176 ns; Loc. = LC_X6_Y3_N0; Fanout = 3; COMB Node = 'I2C_master:i2c\|Equal1~90'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.176 ns" { I2C_master:i2c|count[2] I2C_master:i2c|Equal1~90 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 257 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.462 ns) 2.087 ns I2C_master:i2c\|data_out\[2\]~156 3 COMB LC_X6_Y3_N3 8 " "Info: 3: + IC(0.449 ns) + CELL(0.462 ns) = 2.087 ns; Loc. = LC_X6_Y3_N3; Fanout = 8; COMB Node = 'I2C_master:i2c\|data_out\[2\]~156'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.911 ns" { I2C_master:i2c|Equal1~90 I2C_master:i2c|data_out[2]~156 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 253 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.237 ns) + CELL(0.125 ns) 3.449 ns I2C_master:i2c\|Decoder0~102 4 COMB LC_X7_Y3_N2 1 " "Info: 4: + IC(1.237 ns) + CELL(0.125 ns) = 3.449 ns; Loc. = LC_X7_Y3_N2; Fanout = 1; COMB Node = 'I2C_master:i2c\|Decoder0~102'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.362 ns" { I2C_master:i2c|data_out[2]~156 I2C_master:i2c|Decoder0~102 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 256 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(0.369 ns) 4.277 ns I2C_master:i2c\|data_out\[2\] 5 REG LC_X7_Y3_N5 2 " "Info: 5: + IC(0.459 ns) + CELL(0.369 ns) = 4.277 ns; Loc. = LC_X7_Y3_N5; Fanout = 2; REG Node = 'I2C_master:i2c\|data_out\[2\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.828 ns" { I2C_master:i2c|Decoder0~102 I2C_master:i2c|data_out[2] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 253 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.527 ns ( 35.70 % ) " "Info: Total cell delay = 1.527 ns ( 35.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.750 ns ( 64.30 % ) " "Info: Total interconnect delay = 2.750 ns ( 64.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.277 ns" { I2C_master:i2c|count[2] I2C_master:i2c|Equal1~90 I2C_master:i2c|data_out[2]~156 I2C_master:i2c|Decoder0~102 I2C_master:i2c|data_out[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.277 ns" { I2C_master:i2c|count[2] {} I2C_master:i2c|Equal1~90 {} I2C_master:i2c|data_out[2]~156 {} I2C_master:i2c|Decoder0~102 {} I2C_master:i2c|data_out[2] {} } { 0.000ns 0.605ns 0.449ns 1.237ns 0.459ns } { 0.000ns 0.571ns 0.462ns 0.125ns 0.369ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "I2C_scl destination 4.007 ns + Shortest register " "Info: + Shortest clock path from clock \"I2C_scl\" to destination register is 4.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_scl 1 CLK PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_39; Fanout = 1; CLK Node = 'I2C_scl'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_scl } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.731 ns) 0.731 ns I2C_scl~0 2 COMB IOC_X5_Y0_N3 22 " "Info: 2: + IC(0.000 ns) + CELL(0.731 ns) = 0.731 ns; Loc. = IOC_X5_Y0_N3; Fanout = 22; COMB Node = 'I2C_scl~0'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.731 ns" { I2C_scl I2C_scl~0 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.702 ns) + CELL(0.574 ns) 4.007 ns I2C_master:i2c\|data_out\[2\] 3 REG LC_X7_Y3_N5 2 " "Info: 3: + IC(2.702 ns) + CELL(0.574 ns) = 4.007 ns; Loc. = LC_X7_Y3_N5; Fanout = 2; REG Node = 'I2C_master:i2c\|data_out\[2\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.276 ns" { I2C_scl~0 I2C_master:i2c|data_out[2] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 253 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.305 ns ( 32.57 % ) " "Info: Total cell delay = 1.305 ns ( 32.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.702 ns ( 67.43 % ) " "Info: Total interconnect delay = 2.702 ns ( 67.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.007 ns" { I2C_scl I2C_scl~0 I2C_master:i2c|data_out[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.007 ns" { I2C_scl {} I2C_scl~0 {} I2C_master:i2c|data_out[2] {} } { 0.000ns 0.000ns 2.702ns } { 0.000ns 0.731ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "I2C_scl source 4.007 ns - Longest register " "Info: - Longest clock path from clock \"I2C_scl\" to source register is 4.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_scl 1 CLK PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_39; Fanout = 1; CLK Node = 'I2C_scl'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2C_scl } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.731 ns) 0.731 ns I2C_scl~0 2 COMB IOC_X5_Y0_N3 22 " "Info: 2: + IC(0.000 ns) + CELL(0.731 ns) = 0.731 ns; Loc. = IOC_X5_Y0_N3; Fanout = 22; COMB Node = 'I2C_scl~0'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.731 ns" { I2C_scl I2C_scl~0 } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.702 ns) + CELL(0.574 ns) 4.007 ns I2C_master:i2c\|count\[2\] 3 REG LC_X6_Y3_N8 13 " "Info: 3: + IC(2.702 ns) + CELL(0.574 ns) = 4.007 ns; Loc. = LC_X6_Y3_N8; Fanout = 13; REG Node = 'I2C_master:i2c\|count\[2\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.276 ns" { I2C_scl~0 I2C_master:i2c|count[2] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 218 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.305 ns ( 32.57 % ) " "Info: Total cell delay = 1.305 ns ( 32.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.702 ns ( 67.43 % ) " "Info: Total interconnect delay = 2.702 ns ( 67.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.007 ns" { I2C_scl I2C_scl~0 I2C_master:i2c|count[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.007 ns" { I2C_scl {} I2C_scl~0 {} I2C_master:i2c|count[2] {} } { 0.000ns 0.000ns 2.702ns } { 0.000ns 0.731ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.007 ns" { I2C_scl I2C_scl~0 I2C_master:i2c|data_out[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.007 ns" { I2C_scl {} I2C_scl~0 {} I2C_master:i2c|data_out[2] {} } { 0.000ns 0.000ns 2.702ns } { 0.000ns 0.731ns 0.574ns } "" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.007 ns" { I2C_scl I2C_scl~0 I2C_master:i2c|count[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.007 ns" { I2C_scl {} I2C_scl~0 {} I2C_master:i2c|count[2] {} } { 0.000ns 0.000ns 2.702ns } { 0.000ns 0.731ns 0.574ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 218 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 253 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 218 -1 0 } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 253 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.277 ns" { I2C_master:i2c|count[2] I2C_master:i2c|Equal1~90 I2C_master:i2c|data_out[2]~156 I2C_master:i2c|Decoder0~102 I2C_master:i2c|data_out[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.277 ns" { I2C_master:i2c|count[2] {} I2C_master:i2c|Equal1~90 {} I2C_master:i2c|data_out[2]~156 {} I2C_master:i2c|Decoder0~102 {} I2C_master:i2c|data_out[2] {} } { 0.000ns 0.605ns 0.449ns 1.237ns 0.459ns } { 0.000ns 0.571ns 0.462ns 0.125ns 0.369ns } "" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.007 ns" { I2C_scl I2C_scl~0 I2C_master:i2c|data_out[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.007 ns" { I2C_scl {} I2C_scl~0 {} I2C_master:i2c|data_out[2] {} } { 0.000ns 0.000ns 2.702ns } { 0.000ns 0.731ns 0.574ns } "" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.007 ns" { I2C_scl I2C_scl~0 I2C_master:i2c|count[2] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.007 ns" { I2C_scl {} I2C_scl~0 {} I2C_master:i2c|count[2] {} } { 0.000ns 0.000ns 2.702ns } { 0.000ns 0.731ns 0.574ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "I2C_sda " "Info: No valid register-to-register data paths exist for clock \"I2C_sda\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "SPI_cs " "Info: No valid register-to-register data paths exist for clock \"SPI_cs\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "SPI_slave:spi\|data_in\[1\] SPI_mosi SPI_sclk 1.135 ns register " "Info: tsu for register \"SPI_slave:spi\|data_in\[1\]\" (data pin = \"SPI_mosi\", clock pin = \"SPI_sclk\") is 1.135 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.053 ns + Longest pin register " "Info: + Longest pin to register delay is 5.053 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.731 ns) 0.731 ns SPI_mosi 1 PIN PIN_92 16 " "Info: 1: + IC(0.000 ns) + CELL(0.731 ns) = 0.731 ns; Loc. = PIN_92; Fanout = 16; PIN Node = 'SPI_mosi'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_mosi } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.583 ns) + CELL(0.739 ns) 5.053 ns SPI_slave:spi\|data_in\[1\] 2 REG LC_X5_Y3_N2 2 " "Info: 2: + IC(3.583 ns) + CELL(0.739 ns) = 5.053 ns; Loc. = LC_X5_Y3_N2; Fanout = 2; REG Node = 'SPI_slave:spi\|data_in\[1\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.322 ns" { SPI_mosi SPI_slave:spi|data_in[1] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.470 ns ( 29.09 % ) " "Info: Total cell delay = 1.470 ns ( 29.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.583 ns ( 70.91 % ) " "Info: Total interconnect delay = 3.583 ns ( 70.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.053 ns" { SPI_mosi SPI_slave:spi|data_in[1] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.053 ns" { SPI_mosi {} SPI_mosi~combout {} SPI_slave:spi|data_in[1] {} } { 0.000ns 0.000ns 3.583ns } { 0.000ns 0.731ns 0.739ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 98 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SPI_sclk destination 4.126 ns - Shortest register " "Info: - Shortest clock path from clock \"SPI_sclk\" to destination register is 4.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.047 ns) 1.047 ns SPI_sclk 1 CLK PIN_96 26 " "Info: 1: + IC(0.000 ns) + CELL(1.047 ns) = 1.047 ns; Loc. = PIN_96; Fanout = 26; CLK Node = 'SPI_sclk'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SPI_sclk } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.505 ns) + CELL(0.574 ns) 4.126 ns SPI_slave:spi\|data_in\[1\] 2 REG LC_X5_Y3_N2 2 " "Info: 2: + IC(2.505 ns) + CELL(0.574 ns) = 4.126 ns; Loc. = LC_X5_Y3_N2; Fanout = 2; REG Node = 'SPI_slave:spi\|data_in\[1\]'" {  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.079 ns" { SPI_sclk SPI_slave:spi|data_in[1] } "NODE_NAME" } } { "../code/SPI_to_I2C.v" "" { Text "U:/Work/MAXIIZ Design Examples/Designs/AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example/code/SPI_to_I2C.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.621 ns ( 39.29 % ) " "Info: Total cell delay = 1.621 ns ( 39.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.505 ns ( 60.71 % ) " "Info: Total interconnect delay = 2.505 ns ( 60.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.126 ns" { SPI_sclk SPI_slave:spi|data_in[1] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.126 ns" { SPI_sclk {} SPI_sclk~combout {} SPI_slave:spi|data_in[1] {} } { 0.000ns 0.000ns 2.505ns } { 0.000ns 1.047ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.053 ns" { SPI_mosi SPI_slave:spi|data_in[1] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.053 ns" { SPI_mosi {} SPI_mosi~combout {} SPI_slave:spi|data_in[1] {} } { 0.000ns 0.000ns 3.583ns } { 0.000ns 0.731ns 0.739ns } "" } } { "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "v:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.126 ns" { SPI_sclk SPI_slave:spi|data_in[1] } "NODE_NAME" } } { "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "v:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.126 ns" { SPI_sclk {} SPI_sclk~combout {} SPI_slave:spi|data_in[1] {} } { 0.000ns 0.000ns 2.505ns } { 0.000ns 1.047ns 0.574ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}