mcu_ctrl.rpt

基于等精度测频原理

Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              d:\cpld\mcu_ctrl.rpt
mcu_ctrl

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

           Logic cells placed in LAB 'B'
        +- LC25 Lcd2En
        | 
        |   Other LABs fed by signals
        |   that feed LAB 'B'
LC      | | A B C D |     Logic cells that feed LAB 'B':

Pin
43   -> - | - - - * | <-- ALE
1    -> * | - * - * | <-- P27
44   -> * | - * - * | <-- RD
2    -> * | - * - * | <-- WR
LC50 -> * | - * - * | <-- |74373:112|:12
LC54 -> * | - * - * | <-- |74373:112|:13
LC51 -> * | - * - * | <-- |74373:112|:14
LC52 -> * | - * - * | <-- |74373:112|:15


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              d:\cpld\mcu_ctrl.rpt
mcu_ctrl

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                           Logic cells placed in LAB 'D'
        +----------------- LC64 Lcd1En
        | +--------------- LC62 Y0
        | | +------------- LC57 Y1
        | | | +----------- LC53 Y2
        | | | | +--------- LC49 Y3
        | | | | | +------- LC50 |74373:112|:12
        | | | | | | +----- LC54 |74373:112|:13
        | | | | | | | +--- LC51 |74373:112|:14
        | | | | | | | | +- LC52 |74373:112|:15
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC50 -> * * * * * * - - - | - * - * | <-- |74373:112|:12
LC54 -> * * * * * - * - - | - * - * | <-- |74373:112|:13
LC51 -> * * * * * - - * - | - * - * | <-- |74373:112|:14
LC52 -> * * * * * - - - * | - * - * | <-- |74373:112|:15

Pin
43   -> - - - - - * * * * | - - - * | <-- ALE
17   -> - - - - - * - - - | - - - * | <-- P00
18   -> - - - - - - * - - | - - - * | <-- P01
19   -> - - - - - - - * - | - - - * | <-- P02
20   -> - - - - - - - - * | - - - * | <-- P03
1    -> * * * * * - - - - | - * - * | <-- P27
44   -> * * * * * - - - - | - * - * | <-- RD
2    -> * - - - - - - - - | - * - * | <-- WR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              d:\cpld\mcu_ctrl.rpt
mcu_ctrl

** EQUATIONS **

ALE      : INPUT;
P00      : INPUT;
P01      : INPUT;
P02      : INPUT;
P03      : INPUT;
P04      : INPUT;
P05      : INPUT;
P06      : INPUT;
P07      : INPUT;
P27      : INPUT;
RD       : INPUT;
WR       : INPUT;

-- Node name is 'Lcd1En' 
-- Equation name is 'Lcd1En', location is LC064, type is output.
 Lcd1En  = LCELL( _EQ001 $  GND);
  _EQ001 = !_LC050 & !_LC051 &  _LC052 &  _LC054 &  P27 & !WR
         # !_LC050 & !_LC051 &  _LC052 &  _LC054 &  P27 & !RD;

-- Node name is 'Lcd2En' 
-- Equation name is 'Lcd2En', location is LC025, type is output.
 Lcd2En  = LCELL( _EQ002 $  GND);
  _EQ002 =  _LC050 & !_LC051 &  _LC052 &  _LC054 &  P27 & !WR
         #  _LC050 & !_LC051 &  _LC052 &  _LC054 &  P27 & !RD;

-- Node name is 'Y0' 
-- Equation name is 'Y0', location is LC062, type is output.
 Y0      = LCELL( _EQ003 $  GND);
  _EQ003 = !_LC050 & !_LC051 & !_LC052 & !_LC054 &  P27 & !RD;

-- Node name is 'Y1' 
-- Equation name is 'Y1', location is LC057, type is output.
 Y1      = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC050 & !_LC051 & !_LC052 & !_LC054 &  P27 & !RD;

-- Node name is 'Y2' 
-- Equation name is 'Y2', location is LC053, type is output.
 Y2      = LCELL( _EQ005 $  GND);
  _EQ005 = !_LC050 & !_LC051 & !_LC052 &  _LC054 &  P27 & !RD;

-- Node name is 'Y3' 
-- Equation name is 'Y3', location is LC049, type is output.
 Y3      = LCELL( _EQ006 $  GND);
  _EQ006 =  _LC050 & !_LC051 & !_LC052 &  _LC054 &  P27 & !RD;

-- Node name is '|74373:112|:12' 
-- Equation name is '_LC050', type is buried 
_LC050   = LCELL( _EQ007 $  GND);
  _EQ007 =  ALE &  P00
         #  _LC050 &  P00
         # !ALE &  _LC050;

-- Node name is '|74373:112|:13' 
-- Equation name is '_LC054', type is buried 
_LC054   = LCELL( _EQ008 $  GND);
  _EQ008 =  ALE &  P01
         #  _LC054 &  P01
         # !ALE &  _LC054;

-- Node name is '|74373:112|:14' 
-- Equation name is '_LC051', type is buried 
_LC051   = LCELL( _EQ009 $  GND);
  _EQ009 =  ALE &  P02
         #  _LC051 &  P02
         # !ALE &  _LC051;

-- Node name is '|74373:112|:15' 
-- Equation name is '_LC052', type is buried 
_LC052   = LCELL( _EQ010 $  GND);
  _EQ010 =  ALE &  P03
         #  _LC052 &  P03
         # !ALE &  _LC052;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       d:\cpld\mcu_ctrl.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,380K