colorbar.tan.rpt

这个试验要配合EDA4.0底板一起使用.先将核心板插在EDA4.0底板上面,然后接上VGA显示器. 1。源文件保存在src目录

+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+
; Type                                                       ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                  ; To                                                                    ; From Clock                                  ; To Clock                                    ; Failed Paths ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+
; Worst-case tco                                             ; N/A      ; None                             ; 10.358 ns                        ; vga_vl:inst|lpm_counter:hcnt_rtl_0|cntr_gq7:auto_generated|safe_q[3]  ; VGA_RGB[1]                                                            ; clk                                         ;                                             ; 0            ;
; Clock Setup: 'VGA_PLL:inst4|altpll:altpll_component|_clk0' ; 3.190 ns ; 40.00 MHz ( period = 25.000 ns ) ; 53.71 MHz ( period = 18.620 ns ) ; vga_vl:inst|lpm_counter:vcnt_rtl_1|cntr_gq7:auto_generated|safe_q[6]  ; vga_vl:inst|enable                                                    ; VGA_PLL:inst4|altpll:altpll_component|_clk0 ; VGA_PLL:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'VGA_PLL:inst4|altpll:altpll_component|_clk0'  ; 1.073 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; vga_vl:inst|lpm_counter:vcnt_rtl_1|cntr_gq7:auto_generated|safe_q[10] ; vga_vl:inst|lpm_counter:vcnt_rtl_1|cntr_gq7:auto_generated|safe_q[10] ; VGA_PLL:inst4|altpll:altpll_component|_clk0 ; VGA_PLL:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                               ;          ;                                  ;                                  ;                                                                       ;                                                                       ;                                             ;                                             ; 0            ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                ;
+---------------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+
; Clock Node Name                             ; Clock Setting Name ; Type       ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ;
+---------------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+
; VGA_PLL:inst4|altpll:altpll_component|_clk0 ;                    ; PLL output ; 40.0 MHz         ; clk      ; 4                     ; 5                   ; -1.885 ns ;
; clk                                         ;                    ; User Pin   ; 50.0 MHz         ; NONE     ; N/A                   ; N/A                 ; N/A       ;
+---------------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+