📄 colorbar.map.rpt
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; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; vga_vl:inst|hsyncint ; 13 ;
; vga_vl:inst|vsync ; 1 ;
; Total number of inverted registers = 2 ; ;
+----------------------------------------+---------+
+-----------+
; Hierarchy ;
+-----------+
ColorBar
|-- vga_vl:inst
|-- lpm_counter:hcnt_rtl_0
|-- cntr_gq7:auto_generated
|-- lpm_counter:vcnt_rtl_1
|-- cntr_gq7:auto_generated
|-- VGA_PLL:inst4
|-- altpll:altpll_component
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
; |ColorBar ; 65 (0) ; 25 ; 0 ; 7 ; 0 ; 40 (0) ; 0 (0) ; 25 (0) ; 22 (0) ; |ColorBar ;
; |VGA_PLL:inst4| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |ColorBar|VGA_PLL:inst4 ;
; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |ColorBar|VGA_PLL:inst4|altpll:altpll_component ;
; |vga_vl:inst| ; 65 (43) ; 25 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 25 (3) ; 22 (0) ; |ColorBar|vga_vl:inst ;
; |lpm_counter:hcnt_rtl_0| ; 11 (0) ; 11 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (0) ; 11 (0) ; |ColorBar|vga_vl:inst|lpm_counter:hcnt_rtl_0 ;
; |cntr_gq7:auto_generated| ; 11 (11) ; 11 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; 11 (11) ; |ColorBar|vga_vl:inst|lpm_counter:hcnt_rtl_0|cntr_gq7:auto_generated ;
; |lpm_counter:vcnt_rtl_1| ; 11 (0) ; 11 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (0) ; 11 (0) ; |ColorBar|vga_vl:inst|lpm_counter:vcnt_rtl_1 ;
; |cntr_gq7:auto_generated| ; 11 (11) ; 11 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; 11 (11) ; |ColorBar|vga_vl:inst|lpm_counter:vcnt_rtl_1|cntr_gq7:auto_generated ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA/HSNIOSV4.0/ep1c6/S5_VGA/Proj/ColorBar.map.eqn.
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; ../src/vga_vl.v ; yes ; E:/EDA/HSNIOSV4.0/ep1c6/S5_VGA/src/vga_vl.v ;
; ../Src/ColorBar.bdf ; yes ; E:/EDA/HSNIOSV4.0/ep1c6/S5_VGA/Src/ColorBar.bdf ;
; VGA_PLL.v ; yes ; E:/EDA/HSNIOSV4.0/ep1c6/S5_VGA/Proj/VGA_PLL.v ;
; altpll.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/altpll.tdf ;
; aglobal42.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc ;
; stratix_pll.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/cycloneii_pll.inc ;
; lpm_counter.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; db/cntr_gq7.tdf ; yes ; E:/EDA/HSNIOSV4.0/ep1c6/S5_VGA/Proj/db/cntr_gq7.tdf ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 65 ;
; Total combinational functions ; 65 ;
; Total 4-input functions ; 31 ;
; Total 3-input functions ; 6 ;
; Total 2-input functions ; 6 ;
; Total 1-input functions ; 22 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 25 ;
; Total logic cells in carry chains ; 22 ;
; I/O pins ; 7 ;
; Total PLLs ; 1 ;
; Maximum fan-out node ; rst ;
; Maximum fan-out ; 25 ;
; Total fan-out ; 274 ;
; Average fan-out ; 3.75 ;
+-----------------------------------+---------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version
Info: Processing started: Fri Jun 02 12:33:44 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off ColorBar -c ColorBar
Info: Found 1 design units, including 1 entities, in source file ../src/vga_vl.v
Info: Found entity 1: vga_vl
Info: Found 1 design units, including 1 entities, in source file ../Src/ColorBar.bdf
Info: Found entity 1: ColorBar
Warning: Can't find a definition for parameter H_PIXELS -- assuming 32'b00000000000000000000001100100110 was intended to be a quoted string
Warning: Can't find a definition for parameter H_FRONTPORCH -- assuming 32'b00000000000000000000000000100101 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCTIME -- assuming 32'b00000000000000000000000010000000 was intended to be a quoted string
Warning: Can't find a definition for parameter H_BACKPORCH -- assuming 32'b00000000000000000000000001010101 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCSTART -- assuming 32'b00000000000000000000001101001011 was intended to be a quoted string
Warning: Can't find a definition for parameter H_SYNCEND -- assuming 32'b00000000000000000000001111001011 was intended to be a quoted string
Warning: Can't find a definition for parameter H_PERIOD -- assuming 32'b00000000000000000000010000100000 was intended to be a quoted string
Warning: Can't find a definition for parameter V_LINES -- assuming 32'b00000000000000000000001001011100 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCTIME -- assuming 32'b00000000000000000000000000000100 was intended to be a quoted string
Warning: Can't find a definition for parameter V_BACKPORCH -- assuming 32'b00000000000000000000000000010101 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCSTART -- assuming 32'b00000000000000000000001001011011 was intended to be a quoted string
Warning: Can't find a definition for parameter V_SYNCEND -- assuming 32'b00000000000000000000001001011111 was intended to be a quoted string
Warning: Can't find a definition for parameter V_PERIOD -- assuming 32'b00000000000000000000001001110100 was intended to be a quoted string
Warning: Verilog HDL assignment warning at vga_vl.v(98): truncated value with size 12 to match size of target (11)
Warning: Verilog HDL assignment warning at vga_vl.v(119): truncated value with size 12 to match size of target (11)
Info: Using design file VGA_PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: VGA_PLL
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Inferred 2 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: "vga_vl:inst|hcnt[0]~22"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: "vga_vl:inst|vcnt[0]~22"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_gq7.tdf
Info: Found entity 1: cntr_gq7
Info: Registers with preset signals will power-up high
Info: Implemented 73 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 5 output pins
Info: Implemented 65 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
Info: Processing ended: Fri Jun 02 12:34:00 2006
Info: Elapsed time: 00:00:17
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