dsp28_xintf.c

这是在DSP 的基础上扩展10M以太网来实现网络的通讯,用的CPU 为2812

//
//      TMDX ALPHA RELEASE
//      Intended for product evaluation purposes
//
//###########################################################################
//
// FILE:	DSP28_Xintf.c
//
// TITLE:	DSP28 Device External Interface Init & Support Functions.
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
//  0.56| 20 May 2002 | L.H. | No change
//  0.57| 27 May 2002 | L.H. | No change
//###########################################################################

#include "DSP28_Device.h"

//---------------------------------------------------------------------------
// InitXINTF: 
//---------------------------------------------------------------------------
// This function initializes the External Interface to a known state.
//
void InitXintf(void)
{

    //XintfRegs.XINTCNF2.bit.XTIMCLK = 1;  // XTIMCLK = SYSCLKOUT/2
	XintfRegs.XINTCNF2.bit.XTIMCLK = 0;  // XTIMCLK = SYSCLKOUT
    XintfRegs.XINTCNF2.bit.CLKOFF = 1;   // DISABLE XCLKOUT
	XintfRegs.XINTCNF2.bit.WRBUFF = 0;   // NO WRITE BUFFER
	//XintfRegs.XINTCNF2.bit.CLKMODE = 1;  // XCLKOUT = SYSCLKOUT/4
	XintfRegs.XINTCNF2.bit.CLKMODE = 0;

	// Zone 0
	// Ignore XREADY for Zone 1 accesses
	// Change read access lead/active/trail timing
	XintfRegs.XTIMING0.bit.USEREADY = 0;
	XintfRegs.XTIMING0.bit.XSIZE = 3;		// ALWAYS WRITE TO 11BIT
	XintfRegs.XTIMING0.bit.XWRLEAD=1;//lead阶段不能设为0，否则程序不能运行。
	XintfRegs.XTIMING0.bit.XWRACTIVE = 1;
	XintfRegs.XTIMING0.bit.XWRTRAIL=1;//设为0时发送有误
	XintfRegs.XTIMING0.bit.XRDLEAD = 1;
	XintfRegs.XTIMING0.bit.XRDACTIVE =2;
	XintfRegs.XTIMING0.bit.XRDTRAIL = 0;//此处必须设为0，设为1时接收间隔性丢包，主要是8019头四个字节中的下一帧地址错误

	// Double lead/active/trial timing for Zone 0
	//XintfRegs.XTIMING0.bit.X2TIMING=1;
	XintfRegs.XTIMING0.bit.X2TIMING=0;

	// Zone 1
	// Ignore XREADY for Zone 1 accesses
	// Change read access lead/active/trail timing
	XintfRegs.XTIMING1.bit.USEREADY = 1;
	XintfRegs.XTIMING1.bit.XSIZE = 3;		// ALWAYS WRITE TO 11BIT
	XintfRegs.XTIMING1.bit.XWRACTIVE = 3;
	XintfRegs.XTIMING1.bit.XWRTRAIL=7;
	XintfRegs.XTIMING1.bit.XWRLEAD=3;
	XintfRegs.XTIMING1.bit.XRDLEAD = 3;
	XintfRegs.XTIMING1.bit.XRDACTIVE =7;
	XintfRegs.XTIMING1.bit.XRDTRAIL = 3;
	// Double lead/active/trial timing for Zone 1
	XintfRegs.XTIMING1.bit.X2TIMING=1;

	
    XintfRegs.XBANK.bit.BCYC = 7; 	
    XintfRegs.XBANK.bit.BANK = 0;
	

	// Zone 2
	// Ignore XREADY for Zone 2 accesses
	// Change read access lead/active/trail timing
	XintfRegs.XTIMING2.bit.USEREADY = 1;
	XintfRegs.XTIMING2.bit.XSIZE = 3;
	XintfRegs.XTIMING2.bit.XWRACTIVE = 1;
	XintfRegs.XTIMING2.bit.XWRTRAIL=3;
	XintfRegs.XTIMING2.bit.XWRLEAD=1;
	XintfRegs.XTIMING2.bit.XRDLEAD = 1;
	XintfRegs.XTIMING2.bit.XRDACTIVE =3;
	XintfRegs.XTIMING2.bit.XRDTRAIL = 1;
	//no Double lead/active/trial timing for Zone 2
	XintfRegs.XTIMING2.bit.X2TIMING=0;

	
	// Zone 6
	// Ignore XREADY for Zone 2 accesses
	// Change read access lead/active/trail timing
	XintfRegs.XTIMING6.bit.USEREADY = 0;
	XintfRegs.XTIMING6.bit.XSIZE = 3;
	XintfRegs.XTIMING6.bit.XWRACTIVE = 1;
	XintfRegs.XTIMING6.bit.XWRTRAIL=1;
	XintfRegs.XTIMING6.bit.XWRLEAD=1;
	XintfRegs.XTIMING6.bit.XRDLEAD = 1;
	XintfRegs.XTIMING6.bit.XRDACTIVE =1;
	XintfRegs.XTIMING6.bit.XRDTRAIL = 1;
	XintfRegs.XTIMING6.bit.X2TIMING=0;
	
   
}	
	
//===========================================================================
// No more.
//===========================================================================