onehot.vhd

design compile synthesis user guide

 Library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.std_logic_arith.all;

 entity ONEHOT is

      Port ( clk : In    std_logic;
             reset : In    std_logic;
             count : BUFFER UNSIGNED (15 downto 0));
 end ONEHOT;

 architecture BEHAVIORAL of ONEHOT is
	signal count15 :std_logic;
	begin

	process(count)
	begin
	count15 <= count(15);
	end process;
	
	process(reset,clk,count)
	begin
	if (reset = '0') then
		count <= "0000000000000001";
	elsif (clk'event and clk = '1')then
			count <= SHL(count, UNSIGNED'("1"));
			count(0) <= count15;
	end if;
	end process;
 end BEHAVIORAL;

configuration CFG_ONEHOT_BLOCK_BEHAVIORAL of ONEHOT is
        for BEHAVIORAL
 
        end for;
 
end CFG_ONEHOT_BLOCK_BEHAVIORAL;