tb_onehot.vhd

design compile synthesis user guide

 use STD.textio.all;
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.std_logic_textio.all;
 use IEEE.std_logic_arith.all;
 use WORK.constants.all;
 
 
 entity E is
 end E;
 
 Architecture A of E is


    component ONEHOT
       Port (   clk : In    std_logic;
                reset : In    std_logic;
                count: buffer unsigned (15 downto 0));
    end component;
 
    signal reset : std_logic;
    signal clk : std_logic;
    signal count_0_port, count_1_port,count_2_port,count_3_port: std_logic;
    signal count_4_port, count_5_port,count_6_port,count_7_port: std_logic;
    signal count_8_port, count_9_port,count_10_port,count_11_port: std_logic;
    signal count_12_port, count_13_port,count_14_port,count_15_port: std_logic;
    signal temp : unsigned(15 downto 0);
    signal flag : std_logic;

 begin
 
 (count_15_port, count_14_port,count_13_port,count_12_port, 
 count_11_port, count_10_port,count_9_port,count_8_port, 
 count_7_port, count_6_port,count_5_port,count_4_port, 
 count_3_port, count_2_port,count_1_port,count_0_port) <= temp;
 
    UUT : onehot
 Port Map ( clk,reset,temp);
 
 -- *** Test Bench - User Defined Section ***
    TB : block
    begin
 
    STIMULUS_RESPONSE : process
 
    file TV : TEXT is in "onehot.tv";
    variable L : LINE;
    variable reset_in : std_logic;
    variable count_3_port_in, count_2_port_in, count_1_port_in, count_0_port_in: std_logic ;
    variable count_4_port_in, count_5_port_in, count_6_port_in, count_7_port_in: std_logic;
    variable count_8_port_in, count_9_port_in, count_10_port_in, count_11_port_in: std_logic;
    variable count_12_port_in, count_13_port_in, count_14_port_in, count_15_port_in: std_logic;
 
        begin
  	 --Get a vector
	 if flag = '1' then wait; end if;
  	 readline (TV,L);
  	 read (L,reset_in);
         read (L,count_15_port_in);
         read (L,count_14_port_in);
         read (L,count_13_port_in);
         read (L,count_12_port_in);
         read (L,count_11_port_in);
         read (L,count_10_port_in);
         read (L,count_9_port_in);
         read (L,count_8_port_in);
         read (L,count_7_port_in);
         read (L,count_6_port_in);
         read (L,count_5_port_in);
         read (L,count_4_port_in);
         read (L,count_3_port_in);
         read (L,count_2_port_in);
         read (L,count_1_port_in);
         read (L,count_0_port_in);

  	 if endfile(TV) then flag <= '1'; end if;
  
     --Synchronize
     clk <= '0';
     wait for HALF_PERIOD - SETTLING_TIME;
 
 	--Assign input values
 	reset <= reset_in;
     --Clock edge
     wait for SETTLING_TIME;
     
     clk <= '1';
     wait for HALF_PERIOD - SETTLING_TIME;
 
     --Check output values
     assert count_0_port = count_0_port_in
     report "Unexpected value on count_0_port" severity error;
     assert count_1_port = count_1_port_in
     report "Unexpected value on count_1_port" severity error;
     assert count_2_port = count_2_port_in
     report "Unexpected value on count_2_port" severity error;
     assert count_3_port = count_3_port_in
     report "Unexpected value on count_3_port" severity error;
     assert count_4_port = count_4_port_in
     report "Unexpected value on count_4_port" severity error;
     assert count_5_port = count_5_port_in
     report "Unexpected value on count_5_port" severity error;
     assert count_6_port = count_6_port_in
     report "Unexpected value on count_6_port" severity error;
     assert count_7_port = count_7_port_in
     report "Unexpected value on count_7_port" severity error;
     assert count_8_port = count_8_port_in
     report "Unexpected value on count_8_port" severity error;
     assert count_9_port = count_9_port_in
     report "Unexpected value on count_9_port" severity error;
     assert count_10_port = count_10_port_in
     report "Unexpected value on count_10_port" severity error;
     assert count_11_port = count_11_port_in
     report "Unexpected value on count_11_port" severity error;
     assert count_12_port = count_12_port_in
     report "Unexpected value on count_12_port" severity error;
     assert count_13_port = count_13_port_in
     report "Unexpected value on count_13_port" severity error;
     assert count_14_port = count_14_port_in
     report "Unexpected value on count_14_port" severity error;
     assert count_15_port = count_15_port_in
     report "Unexpected value on count_15_port" severity error;
 
       --Synchronize
       if flag = '1' then clk <= '0'; end if;
       wait for SETTLING_TIME;
 
       end process;
 
    end block;
 -- *** End Test Bench - User Defined Section ***
 
 end A;
 
 configuration CFG_TB_ONEHOT_BLOCK_BEHAVIORAL of E is
    for A
	for UUT : ONEHOT
		use configuration  WORK.CFG_ONEHOT_BLOCK_BEHAVIORAL;
	end for;
    end for;
 end CFG_TB_ONEHOT_BLOCK_BEHAVIORAL;

--configuration CFG_TB_ONEHOT_BLOCK_NETLIST of E is
--   for A
--	for UUT : ONEHOT
--		use configuration  WORK.CFG_ONEHOT_BLOCK_NETLIST;
--	end for;
--   end for;
-- end CFG_TB_ONEHOT_BLOCK_NETLIST;
 
 -- *** User Defined Configuration ***
--       for TB
 --      end for;
 -- *** End User Defined Configuration ***