onehot.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 28 行

 module onehot(clk, reset, enable, count) ;
 input clk, reset, enable ;
 output [15:0]count ;

 reg [15:0]count ;
 reg count0;

 always @(count)
    begin
    count0 = count[0];
    end 

 always @(posedge clk or negedge reset)
    begin
    if (!reset) count = 16'h8000 ;
    else if (enable)
        begin
        count = count >> 1 ;
        count[15] = count0 ; 
         end
    else count = count ;
    end

 endmodule