report_power.cell

来自「design compile synthesis user guide」· CELL 代码 · 共 51 行

 
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Report : power
	-cell
	-analysis_effort low
	-include_boundary_nets
	-sort_mode cell_internal_power
Design : RIPPLE
Version: v3.2a-development
Date   : Wed Nov 30 23:25:10 1994
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Library(s) Used:

    class (File: /remote/cae3/ashu/DesignPower/DP_Tutorial/lib/class.db)


Operating Conditions: WCCOM   Library: class
Wire Loading Model Mode: top

Design           Wire Loading Model      Library
------------------------------------------------
RIPPLE                 10x10             class


Global Operating Voltage = 4.75 
Power-specific unit information :
    Voltage Units = 1V
    Capacitance Units = 0.100000ff
    Time Units = 1ns
    Dynamic Power Units = 100nW    (derived from V,C,T units)
    Leakage Power Units = 1nW



  Attributes
  ----------
      h  -  Hierarchical cell

                        Cell      Driven Net  Tot Dynamic      Cell
                        Internal  Switching   Power            Leakage
Cell                    Power     Power       (% Cell/Tot)     Power      Attrs
--------------------------------------------------------------------------------
count_reg[0]               0.8946    2.3548      3.249 (28%)      1.0000   
count_reg24[1]             0.8267    1.1425      1.969 (42%)      1.0000   
count_reg40[2]             0.4147    0.5732      0.988 (42%)      1.0000   
count_reg56[3]             0.2462    0.2129      0.459 (54%)      1.0000   
--------------------------------------------------------------------------------
Totals (4 cells)         238.222nW 428.336nW   666.558nW (36%)    4.000nW