quick_map.scr

来自「design compile synthesis user guide」· SCR 代码 · 共 15 行

analyze -format vhdl -lib WORK ripple.vhd
elaborate CFG_RIPPLE_BLOCK_BEHAVIORAL -lib DEFAULT -update
/* set wire load model and apply load at output ports*/
create_clock clk -name clock -period 10
set_operating_conditions -library "class" "WCCOM"
set_wire_load "10x10"
set_driving_cell -cell AN2P -library class all_inputs()
set_load 1 all_outputs()
compile -map_effort low


/* This step added for CPS compliance */
include seq_output.ssa