run.syn.scr

来自「design compile synthesis user guide」· SCR 代码 · 共 22 行

analyze -format vhdl -lib WORK ripple.vhd
elaborate CFG_RIPPLE_BLOCK_BEHAVIORAL -lib DEFAULT -update
write -f db -h -o ../db/ripple.read.db
set_operating_conditions -library "class" "WCCOM"
set_wire_load "10x10"
set_driving_cell -cell AN2P -library class all_inputs()
set_load 1 all_outputs()
compile -map_effort low
/*include set_switching_activity.scr*/

include set_switching_activity.tv.scr
set_switching_activity -period 20 -toggle_rate 2 -static_prob 0.5 find(port,"clk")

/*report power for the design */
report_power 
report_power -net
report_power -cell


write -f db -h -o ../db/ripple.compiled.db
/*quit*/