ripple.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 60 行

 module RIPPLE (clk, reset, count) ;
 input clk, reset ;

 output [3:0]count ;
 reg[3:0] count;
 reg count0, count1, count2 ;

 always @(count)
    begin
    count0 = count[0] ;
    count1 = count[1] ;
    count2 = count[2] ;
    end

 always @(posedge clk or negedge reset)
    begin
    if (!reset) count[0] = 1'b0 ;
    else
        begin
        if (count[0] == 1'b1) count[0] = 1'b0 ;
        else count[0] = 1'b1 ;
        end
    end

 always @(posedge count0 or negedge reset)
    begin
    if (!reset) count[1] = 1'b0 ;
    else
        begin
        if (count[1] == 1'b1) count[1] = 1'b0 ;
        else count[1] = 1'b1 ;
        end
    end

 always @(posedge count1 or negedge reset)
    begin
    if (!reset) count[2] = 1'b0 ;
    else
        begin
        if (count[2] == 1'b1) count[2] = 1'b0 ;
        else count[2] = 1'b1 ;
        end
    end

 always @(posedge count2 or negedge reset)
    begin
    if (!reset) count[3] = 1'b0 ;
    else 
        begin
        if (count[3] == 1'b1) count[3] = 1'b0 ;
        else count[3] = 1'b1 ;
        end
    end

 endmodule