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design compile synthesis user guide

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                          DesignPower (TM)

              Version v3.2a-development -- Dec 01, 1994
              Copyright (c) 1988-1994 by Synopsys, Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Initializing...
analyze -format vhdl -lib WORK {"binary.vhd"}
Loading db file '/remote/src/syn/h/dev/libraries/syn/standard.sldb'
Loading db file '/remote/src/syn/h/dev/libraries/syn/gtech.db'
Reading in the Synopsys vhdl primitives.
/am/remote/cae3/ashu/DesignPower/DP_Tutorial/binary/gatesim/binary.vhd:
1
elaborate CFG_BINARY_BLOCK_BEHAVIORAL -lib DEFAULT -update

Inferred memory devices in process 
	in routine BINARY line 14 in file
         '/am/remote/cae3/ashu/DesignPower/DP_Tutorial/binary/gatesim/binary.vhd'.
===============================================================================
|      Register Name       |   Type    | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
|        count_reg         | Flip-flop |   4   |  Y  | Y  | N  | N  | N  | N  |
===============================================================================

Loading db file '/remote/cae3/ashu/DesignPower/DP_Tutorial/lib/class.db'
Current design is now 'BINARY'
1
set_operating_conditions -library "class" "WCCOM"
Using operating conditions 'WCCOM' found in library 'class'.
1
set_wire_load  "10x10" -library "class"
Using wire_load model '10x10' found in library 'class'.
1
create_clock -name "clk" -period 20 -waveform {"0" "10"} {"clk"}
Performing create_clock on port 'clk'. 
1
set_clock_skew -propagated -uncertainty 1 "clk"
Performing set_clock_skew on clock 'clk'. 
1
set_fix_hold find(clock, "clk")
Performing set_fix_hold on clock 'clk'. 
1
set_max_area 100
1
set_max_fanout 4 BINARY
Performing set_max_fanout on design 'BINARY'. 
1
set_max_transition 1 BINARY 
Performing set_max_transition on design 'BINARY'. 
1
set_driving_cell -cell AN2P -library class all_inputs()
Performing set_driving_cell on port 'clk'. 
Performing set_driving_cell on port 'reset'. 
1
set_load 1 all_outputs()
Performing set_load on port 'count[3]'. 
Performing set_load on port 'count[2]'. 
Performing set_load on port 'count[1]'. 
Performing set_load on port 'count[0]'. 
1
set_max_fanout 4 "clk"
Performing set_max_fanout on port 'clk'. 
1
set_max_fanout 4 "reset"
Performing set_max_fanout on port 'reset'. 
1
set_max_delay 15 -rise -to { "count[3]" "count[2]" "count[1]" "count[0]" } -from { "clk" }
Performing set_max_delay on port 'count[3]'. 
Performing set_max_delay on port 'count[2]'. 
Performing set_max_delay on port 'count[1]'. 
Performing set_max_delay on port 'count[0]'. 
Performing set_max_delay on port 'clk'. 
1
compile -map_effort high

  Loading target library 'class'
  Loading design 'BINARY'

  Beginning CMOS optimization
  ---------------------------

  Beginning Resource Allocation  (constraint driven)
  -----------------------------
  Structuring 'BINARY'
  Mapping 'BINARY'
  Allocating blocks in 'BINARY'
  Allocating blocks in 'BINARY'

  Beginning Pass 1 Mapping
  ------------------------
  Structuring 'BINARY'
  Mapping 'BINARY'
  Structuring 'DW01_inc_4'
  Mapping 'DW01_inc_4'

  Beginning Mapping Optimizations  (High effort)
  -------------------------------
  Structuring 'BINARY'
  Mapping 'BINARY'

	                                      OPTIMIZATION   DESIGN RULE
	    TRIALS     POWER     DELTA DELAY      COST          COST
	   --------    ------    -----------     ------        ------
	         8
	   --------
	         8


  Fixing Design-Rule Constraints  (max_transition)

	                                      OPTIMIZATION   DESIGN RULE
	    TRIALS     POWER     DELTA DELAY      COST          COST
	   --------    ------    -----------     ------        ------
	        12  20.000000          0.00         0.0           5.8
	         1  20.000000          0.00         0.0           5.8
	        13  21.000000          0.00         0.0           2.8
	         1  21.000000          0.00         0.0           2.8
	        11  22.000000          0.00         0.0           2.0
	         1  22.000000          0.00         0.0           2.0
	        11  24.000000          0.00         0.0           1.0
	         1  24.000000          0.00         0.0           1.0
	         1  24.000000          0.00         0.0           1.0
	        10  25.000000          0.00         0.0           0.6
	         1  25.000000          0.00         0.0           0.6
	        10  26.000000          0.00         0.0           0.2
	         1  26.000000          0.00         0.0           0.2
	        15  26.000000          0.00         0.0           0.0
	         1  25.000000          0.00         0.0           0.0
	         1  24.000000          0.00         0.0           0.0
	         2
	   --------
	        93


  Optimization complete
  ---------------------
  Transferring Design 'BINARY' to database 'BINARY.db'
Current design is 'BINARY'.
1
include change_names.scr
change_names -rules vhdl
Information: Using name rules 'vhdl'. (UIMG-23)
Warning: Variable "bus_naming_style" contains characters that are not defined within the "-allowed" character set in current name rule. They are found in the following type(s) of objects: " port  cell  net " (NMA-14)
Warning: In design BINARY, port bus member 'count[3]' changed to 'count(3)'. (NMA-16)
Warning: In design BINARY, port bus member 'count[2]' changed to 'count(2)'. (NMA-16)
Warning: In design BINARY, port bus member 'count[1]' changed to 'count(1)'. (NMA-16)
Warning: In design BINARY, port bus member 'count[0]' changed to 'count(0)'. (NMA-16)
Information: 18 names changed in design 'BINARY'. (NMA-8)
1
define_name_rules lowercase -restricted "a-z" -type cell
1
change_names -rules lowercase
Information: Using name rules 'lowercase'. (UIMG-23)
Warning: In design BINARY, port bus member 'count(3)' changed to 'count[3]'. (NMA-16)
Warning: In design BINARY, port bus member 'count(2)' changed to 'count[2]'. (NMA-16)
Warning: In design BINARY, port bus member 'count(1)' changed to 'count[1]'. (NMA-16)
Warning: In design BINARY, port bus member 'count(0)' changed to 'count[0]'. (NMA-16)
Information: 8 names changed in design 'BINARY'. (NMA-8)
1

1

vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "IEEE.std_logic_textio.all", "WORK.constants.all", "class.COMPONENTS.all"}
{"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "IEEE.std_logic_textio.all", "WORK.constants.all", "class.COMPONENTS.all"}

vhdlout_single_bit = vector
"vector"
vhdlout_architecture_name = "NETLIST"
"NETLIST"
vhdlout_top_configuration_arch_name = "NETLIST"
"NETLIST"
vhdlout_top_configuration_name = "CFG_BINARY_BLOCK_NETLIST"
"CFG_BINARY_BLOCK_NETLIST"
vhdlout_top_configuration_entity_name = "BINARY"
"BINARY"
vhdlout_write_top_configuration = "TRUE"
"TRUE"

write -format db -hierarchy -output "../db/binary_gatesim.db"
Writing to file /am/remote/cae3/ashu/DesignPower/DP_Tutorial/binary/db/binary_gatesim.db
1
write -format vhdl -hierarchy -output "binary_gatesim.vhd"
1
dc_shell>