binary_gatesim.vhd

design compile synthesis user guide

-- synopsys synthesis_off

library IEEE;
library WORK;
library class;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use WORK.constants.all;
use class.COMPONENTS.all;

package CONV_PACK_BINARY is

-- define attributes
attribute ENUM_ENCODING : STRING;

-- define any necessary types
type UNSIGNED is array (INTEGER range <>) of std_logic;

end CONV_PACK_BINARY;
-- synopsys synthesis_on

library IEEE;
library WORK;
library class;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use WORK.constants.all;
use class.COMPONENTS.all;

use work.CONV_PACK_BINARY.all;

entity BINARY is

   port( clk, reset : in std_logic;  count : buffer std_logic_vector (0 to 3));

end BINARY;

architecture NETLIST of BINARY is

   component IVDAP
      port( A : in std_logic;  Y, Z : out std_logic);
   end component;
   
   component IVA
      port( A : in std_logic;  Z : out std_logic);
   end component;
   
   component IV
      port( A : in std_logic;  Z : out std_logic);
   end component;
   
   component ND2P
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component ND2
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component EO
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component OR2
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component FD2
      port( D, CP, CD : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal count36x3x, count36x2x, count36x1x, count36x0x, countx3x, n150, n140,
      countx2x, n141, n142, n130, countx1x, n143, n131, n144, n132, n145, n133,
      countx0x, n146, n134, n147, n135, n148, n123, n136, n149, n137, n125, 
      n138, n139, n128, n129 : std_logic;

begin
   count <= ( countx3x, countx2x, countx1x, countx0x );
   
   COUNT_REGX2X : FD2 port map( D => count36x2x, CP => clk, CD => n123, Q => 
                           n140, QN => n143);
   COUNT_REGX1X : FD2 port map( D => count36x1x, CP => clk, CD => n138, Q => 
                           n141, QN => n144);
   COUNT_REGX0X : FD2 port map( D => count36x0x, CP => clk, CD => n138, Q => 
                           n142, QN => n145);
   U50 : ND2 port map( A => n132, B => n128, Z => n137);
   U51 : ND2 port map( A => n136, B => n137, Z => count36x2x);
   U52 : IVA port map( A => n130, Z => n133);
   U40 : IV port map( A => n125, Z => n132);
   U41 : IVDAP port map( A => n142, Y => count36x0x, Z => countx0x);
   U42 : IVDAP port map( A => n140, Y => n128, Z => countx2x);
   U43 : EO port map( A => countx1x, B => countx0x, Z => count36x1x);
   U44 : ND2 port map( A => countx3x, B => countx2x, Z => n129);
   U45 : OR2 port map( A => n131, B => n129, Z => n130);
   U46 : ND2 port map( A => countx3x, B => n130, Z => n134);
   U34 : ND2P port map( A => countx0x, B => countx1x, Z => n131);
   U47 : ND2 port map( A => n132, B => countx2x, Z => n135);
   U35 : IVDAP port map( A => n141, Y => n146, Z => countx1x);
   U48 : ND2 port map( A => n134, B => n135, Z => count36x3x);
   U36 : IVDAP port map( A => n139, Y => n147, Z => countx3x);
   U49 : ND2 port map( A => countx2x, B => n131, Z => n136);
   U37 : IVDAP port map( A => reset, Y => n148, Z => n138);
   U38 : IVDAP port map( A => reset, Y => n149, Z => n123);
   U39 : OR2 port map( A => n133, B => n131, Z => n125);
   COUNT_REGX3X : FD2 port map( D => count36x3x, CP => clk, CD => n123, Q => 
                           n139, QN => n150);

end NETLIST;
-- synopsys synthesis_off

use work.CONV_PACK_BINARY.all;

configuration CFG_BINARY_BLOCK_NETLIST of BINARY is
   for NETLIST
--      for all: BINARY
--         use entity WORK.BINARY(NETLIST)
--         port map (clk => clk,
--            reset => reset,
--            count(0) => count(3),
--            count(1) => count(2),
--            count(2) => count(1),
--            count(3) => count(0));
--      end for ;
   end for ;
end CFG_BINARY_BLOCK_NETLIST ;
-- synopsys synthesis_on