gatesyn.scr

design compile synthesis user guide

analyze -format vhdl -lib WORK {"binary.vhd"}
elaborate CFG_BINARY_BLOCK_BEHAVIORAL -lib DEFAULT -update

set_operating_conditions -library "class" "WCCOM"
set_wire_load  "10x10" -library "class"

create_clock -name "clk" -period 20 -waveform {"0" "10"} {"clk"}
set_clock_skew -propagated -uncertainty 1 "clk"
set_fix_hold find(clock, "clk")

set_max_area 100
set_max_fanout 4 BINARY
set_max_transition 1 BINARY 
set_driving_cell -cell AN2P -library class all_inputs()
set_load 1 all_outputs()
set_max_fanout 4 "clk"
set_max_fanout 4 "reset"
set_max_delay 15 -rise -to { "count[3]" "count[2]" "count[1]" "count[0]" } -from { "clk" }
compile -map_effort high
include change_names.scr

vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "IEEE.std_logic_textio.all", "WORK.constants.all", "class.COMPONENTS.all"}

vhdlout_single_bit = vector
vhdlout_architecture_name = "NETLIST"
vhdlout_top_configuration_arch_name = "NETLIST"
vhdlout_top_configuration_name = "CFG_BINARY_BLOCK_NETLIST"
vhdlout_top_configuration_entity_name = "BINARY"
vhdlout_write_top_configuration = "TRUE"

write -format db -hierarchy -output "../db/binary_gatesim.db"
write -format vhdl -hierarchy -output "binary_gatesim.vhd"