quick_map.scr

design compile synthesis user guide

/**************************************************************/
/* Notice: A new tutorial for DesignPower and Power Compiler  */
/* is being developed.  It contains the new features of       */ 
/* DesignPower 1997.08.  To obtain this new tutorial, contact */
/* Steve Lentzen at [e-mail].  Please include    */
/* your Synopsys site ID in your request.                     */
/**************************************************************/


analyze -format vhdl -lib WORK binary.vhd
elaborate CFG_BINARY_BLOCK_BEHAVIORAL -lib DEFAULT -update
/* set wire load model and apply load at output ports*/
create_clock clk -name clock -period 20
set_operating_conditions -library "class" "WCCOM"
set_wire_load "10x10"
set_driving_cell -cell AN2P -library class all_inputs()
set_load 1 all_outputs()
compile -map_effort low

/* This step added for CPS compliance */
include seq_output.ssa