tb_binary.vhd

design compile synthesis user guide

 use STD.textio.all;
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.std_logic_textio.all;
 use IEEE.std_logic_arith.all;
 use WORK.constants.all;
 
 
 entity E is
 end E;
 
 Architecture A of E is


    component binary
       Port (   clk : In    std_logic;
                reset : In    std_logic;
                count: buffer unsigned (0 to 3));
    end component;
 
    signal reset : std_logic;
    signal clk : std_logic;
    signal count_0_port, count_1_port,count_2_port,count_3_port: std_logic;
    signal temp : unsigned(0 to 3);
    signal flag : std_logic;

 begin
 
 (count_0_port, count_1_port,count_2_port,count_3_port) <= temp;
 
    UUT : binary
 Port Map ( clk,reset,temp);
 
 -- *** Test Bench - User Defined Section ***
    TB : block
    begin
 
    STIMULUS_RESPONSE : process
 
    file TV : TEXT is in "binary.tv";
    variable L : LINE;
    variable reset_in : std_logic;
    variable count_3_port_in, count_2_port_in,count_1_port_in,count_0_port_in:
    std_logic ;
 
        begin
  	 --Get a vector
	 if flag = '1' then wait; end if;
  	 readline (TV,L);
  	 read (L,reset_in);
  	 read (L,count_0_port_in);
  	 read (L,count_1_port_in);
  	 read (L,count_2_port_in);
  	 read (L,count_3_port_in);
  	 if endfile(TV) then flag <= '1'; end if;
  
     --Synchronize
     clk <= '0';
     wait for HALF_PERIOD - SETTLING_TIME;
 
 	--Assign input values
 	reset <= reset_in;
     --Clock edge
     wait for SETTLING_TIME;
     
     clk <= '1';
     wait for HALF_PERIOD - SETTLING_TIME;
 
     --Check output values
     assert count_0_port = count_0_port_in
     report "Unexpected value on count_0_port" severity error;
     assert count_1_port = count_1_port_in
     report "Unexpected value on count_1_port" severity error;
     assert count_2_port = count_2_port_in
     report "Unexpected value on count_2_port" severity error;
     assert count_3_port = count_3_port_in
     report "Unexpected value on count_3_port" severity error;
 
       --Synchronize
       if flag = '1' then clk <= '0'; end if;
       wait for SETTLING_TIME;
 
       end process;
 
    end block;
 -- *** End Test Bench - User Defined Section ***
 
 end A;
 
 configuration CFG_TB_BINARY_BLOCK_BEHAVIORAL of E is
    for A
	for UUT : BINARY
		use configuration  WORK.CFG_BINARY_BLOCK_BEHAVIORAL;
	end for;
    end for;
 end CFG_TB_BINARY_BLOCK_BEHAVIORAL;

-- configuration CFG_TB_BINARY_BLOCK_NETLIST of E is
--    for A
--	for UUT : BINARY
--		use configuration  WORK.CFG_BINARY_BLOCK_NETLIST;
--	end for;
--   end for;
-- end CFG_TB_BINARY_BLOCK_NETLIST;
 
 -- *** User Defined Configuration ***
--       for TB
 --      end for;
 -- *** End User Defined Configuration ***