binary.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 17 行

module BINARY(clk, reset, count) ;
input clk, reset ;
output [3:0]count ;

reg [3:0]count ;

always @(posedge clk or negedge reset)
    begin
    if (!reset) count = 4'h0 ;
    else 
        begin
        if (count == 4'hf) count = 4'h0 ;
        else count = count + 4'h1 ;
        end
    end
endmodule