class_components.vhd

design compile synthesis user guide

      tpdCD_Q_F                      :	Time := 0.770 ns;
      tpdCP_Q_R                      :	Time := 1.190 ns;
      tpdCP_Q_F                      :	Time := 1.370 ns;
      tpdCD_QN_R                     :	Time := 0.870 ns;
      tpdCP_QN_R                     :	Time := 1.470 ns;
      tpdCP_QN_F                     :	Time := 1.670 ns;
      tsuD_CP                        :	Time := 0.850 ns;
      thCP_D                         :	Time := 0.400 ns;
      tsuCD_CP                       :	Time := 0.500 ns;
      twCP_H                         :	Time := 1.500 ns;
      twCP_L                         :	Time := 1.500 ns;
      twdD_R                         :	Time := 0.000 ns;
      twdD_F                         :	Time := 0.000 ns;
      twdCP_R                        :	Time := 0.000 ns;
      twdCP_F                        :	Time := 0.000 ns;
      twdCD_R                        :	Time := 0.000 ns;
      twdCD_F                        :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      CP                             :	in    STD_LOGIC;
      CD                             :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QN                             :	out   STD_LOGIC);
end component;


----- Component FD4 -----
component FD4
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdSD_Q_R                      :	Time := 0.890 ns;
      tpdCP_Q_R                      :	Time := 1.090 ns;
      tpdCP_Q_F                      :	Time := 1.450 ns;
      tpdSD_QN_F                     :	Time := 0.720 ns;
      tpdCP_QN_R                     :	Time := 1.790 ns;
      tpdCP_QN_F                     :	Time := 1.570 ns;
      tsuD_CP                        :	Time := 0.900 ns;
      thCP_D                         :	Time := 0.400 ns;
      tsuSD_CP                       :	Time := 0.500 ns;
      twCP_H                         :	Time := 1.500 ns;
      twCP_L                         :	Time := 1.500 ns;
      twdD_R                         :	Time := 0.000 ns;
      twdD_F                         :	Time := 0.000 ns;
      twdCP_R                        :	Time := 0.000 ns;
      twdCP_F                        :	Time := 0.000 ns;
      twdSD_R                        :	Time := 0.000 ns;
      twdSD_F                        :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      D                              :	in    STD_LOGIC;
      CP                             :	in    STD_LOGIC;
      SD                             :	in    STD_LOGIC;
      Q                              :	out   STD_LOGIC;
      QN                             :	out   STD_LOGIC);
end component;


----- Component IV -----
component IV
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.380 ns;
      tpdA_Z_F                       :	Time := 0.150 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component IVA -----
component IVA
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.240 ns;
      tpdA_Z_F                       :	Time := 0.250 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component IVAP -----
component IVAP
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.260 ns;
      tpdA_Z_F                       :	Time := 0.140 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component IVDA -----
component IVDA
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Y_R                       :	Time := 0.550 ns;
      tpdA_Y_F                       :	Time := 0.320 ns;
      tpdA_Z_R                       :	Time := 0.480 ns;
      tpdA_Z_F                       :	Time := 0.670 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      Y                              :	out   STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component IVDAP -----
component IVDAP
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Y_R                       :	Time := 0.400 ns;
      tpdA_Y_F                       :	Time := 0.180 ns;
      tpdA_Z_R                       :	Time := 0.360 ns;
      tpdA_Z_F                       :	Time := 0.530 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      Y                              :	out   STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component IVP -----
component IVP
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.360 ns;
      tpdA_Z_F                       :	Time := 0.160 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component ND2 -----
component ND2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.500 ns;
      tpdA_Z_F                       :	Time := 0.130 ns;
      tpdB_Z_R                       :	Time := 0.500 ns;
      tpdB_Z_F                       :	Time := 0.130 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns;
      twdB_R                         :	Time := 0.000 ns;
      twdB_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component ND2P -----
component ND2P
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.500 ns;
      tpdA_Z_F                       :	Time := 0.160 ns;
      tpdB_Z_R                       :	Time := 0.500 ns;
      tpdB_Z_F                       :	Time := 0.160 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns;
      twdB_R                         :	Time := 0.000 ns;
      twdB_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component NR2 -----
component NR2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.550 ns;
      tpdA_Z_F                       :	Time := 0.250 ns;
      tpdB_Z_R                       :	Time := 0.550 ns;
      tpdB_Z_F                       :	Time := 0.250 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns;
      twdB_R                         :	Time := 0.000 ns;
      twdB_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component NR2P -----
component NR2P
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.560 ns;
      tpdA_Z_F                       :	Time := 0.160 ns;
      tpdB_Z_R                       :	Time := 0.560 ns;
      tpdB_Z_F                       :	Time := 0.160 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns;
      twdB_R                         :	Time := 0.000 ns;
      twdB_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


----- Component OR2 -----
component OR2
-- synopsys translate_off
   generic(
      Timing_mesg: Boolean := Default_Timing_mesg;
      Timing_xgen: Boolean := Default_Timing_xgen;
      tpdA_Z_R                       :	Time := 0.380 ns;
      tpdA_Z_F                       :	Time := 0.850 ns;
      tpdB_Z_R                       :	Time := 0.380 ns;
      tpdB_Z_F                       :	Time := 0.850 ns;
      twdA_R                         :	Time := 0.000 ns;
      twdA_F                         :	Time := 0.000 ns;
      twdB_R                         :	Time := 0.000 ns;
      twdB_F                         :	Time := 0.000 ns);

-- synopsys translate_on
   port(
      A                              :	in    STD_LOGIC;
      B                              :	in    STD_LOGIC;
      Z                              :	out   STD_LOGIC);
end component;


end COMPONENTS;

---- end of components library ----