📄 class_components.vhd
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------------------------------------------------------------------ -- Created by the Synopsys Library Compiler v3.2a-- FILENAME : /am/remote/cae3/ashu/DesignPower/DP_Tutorial/lib/class_components.vhd-- FILE CONTENTS: Component Package-- DATE CREATED : Mon Nov 7 17:06:25 1994-- -- LIBRARY : class-- DATE ENTERED : November 14. 1994-- REVISION : V3.2b-- TECHNOLOGY : cmos-- TIME SCALE : 1 ns-- LOGIC SYSTEM : IEEE-1164-- NOTES : Timing_mesg(TRUE), Timing_xgen(FALSE), GLITCH_HANDLE-- HISTORY :-- ----------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offuse IEEE.GS_TYPES.sdt_values_t;-- synopsys translate_onpackage COMPONENTS isconstant Default_Timing_mesg : Boolean := True;constant Default_Timing_xgen : Boolean := False;----- Component AN2 -----component AN2-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdA_Z_R : Time := 0.480 ns; tpdA_Z_F : Time := 0.770 ns; tpdB_Z_R : Time := 0.480 ns; tpdB_Z_F : Time := 0.770 ns; twdA_R : Time := 0.000 ns; twdA_F : Time := 0.000 ns; twdB_R : Time := 0.000 ns; twdB_F : Time := 0.000 ns);-- synopsys translate_on port( A : in STD_LOGIC; B : in STD_LOGIC; Z : out STD_LOGIC);end component;----- Component AN2P -----component AN2P-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdA_Z_R : Time := 0.540 ns; tpdA_Z_F : Time := 0.840 ns; tpdB_Z_R : Time := 0.540 ns; tpdB_Z_F : Time := 0.840 ns; twdA_R : Time := 0.000 ns; twdA_F : Time := 0.000 ns; twdB_R : Time := 0.000 ns; twdB_F : Time := 0.000 ns);-- synopsys translate_on port( A : in STD_LOGIC; B : in STD_LOGIC; Z : out STD_LOGIC);end component;----- Component B4I -----component B4I-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdA_Z_R : Time := 0.350 ns; tpdA_Z_F : Time := 0.110 ns; twdA_R : Time := 0.000 ns; twdA_F : Time := 0.000 ns);-- synopsys translate_on port( A : in STD_LOGIC; Z : out STD_LOGIC);end component;----- Component B4IP -----component B4IP-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdA_Z_R : Time := 0.350 ns; tpdA_Z_F : Time := 0.020 ns; twdA_R : Time := 0.000 ns; twdA_F : Time := 0.000 ns);-- synopsys translate_on port( A : in STD_LOGIC; Z : out STD_LOGIC);end component;----- Component B5I -----component B5I-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdA_Z_R : Time := 0.360 ns; tpdA_Z_F : Time := 0.120 ns; twdA_R : Time := 0.000 ns; twdA_F : Time := 0.000 ns);-- synopsys translate_on port( A : in STD_LOGIC; Z : out STD_LOGIC);end component;----- Component B5IP -----component B5IP-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdA_Z_R : Time := 0.330 ns; tpdA_Z_F : Time := 0.160 ns; twdA_R : Time := 0.000 ns; twdA_F : Time := 0.000 ns);-- synopsys translate_on port( A : in STD_LOGIC; Z : out STD_LOGIC);end component;----- Component EN -----component EN-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdA_Z_R : Time := 0.790 ns; tpdA_Z_F : Time := 1.060 ns; tpdB_Z_R : Time := 0.790 ns; tpdB_Z_F : Time := 1.060 ns; twdA_R : Time := 0.000 ns; twdA_F : Time := 0.000 ns; twdB_R : Time := 0.000 ns; twdB_F : Time := 0.000 ns);-- synopsys translate_on port( A : in STD_LOGIC; B : in STD_LOGIC; Z : out STD_LOGIC);end component;----- Component EO -----component EO-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdA_Z_R : Time := 0.790 ns; tpdA_Z_F : Time := 1.060 ns; tpdB_Z_R : Time := 0.790 ns; tpdB_Z_F : Time := 1.060 ns; twdA_R : Time := 0.000 ns; twdA_F : Time := 0.000 ns; twdB_R : Time := 0.000 ns; twdB_F : Time := 0.000 ns);-- synopsys translate_on port( A : in STD_LOGIC; B : in STD_LOGIC; Z : out STD_LOGIC);end component;----- Component FD1 -----component FD1-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdCP_Q_R : Time := 1.090 ns; tpdCP_Q_F : Time := 1.370 ns; tpdCP_QN_R : Time := 1.590 ns; tpdCP_QN_F : Time := 1.570 ns; tsuD_CP : Time := 0.800 ns; thCP_D : Time := 0.400 ns; twCP_H : Time := 1.500 ns; twCP_L : Time := 1.500 ns; twdD_R : Time := 0.000 ns; twdD_F : Time := 0.000 ns; twdCP_R : Time := 0.000 ns; twdCP_F : Time := 0.000 ns);-- synopsys translate_on port( D : in STD_LOGIC; CP : in STD_LOGIC; Q : out STD_LOGIC; QN : out STD_LOGIC);end component;----- Component FD1P -----component FD1P-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdCP_Q_R : Time := 1.160 ns; tpdCP_Q_F : Time := 1.440 ns; tpdCP_QN_R : Time := 1.840 ns; tpdCP_QN_F : Time := 1.740 ns; tsuD_CP : Time := 0.800 ns; thCP_D : Time := 0.400 ns; twCP_H : Time := 1.500 ns; twCP_L : Time := 1.500 ns; twdD_R : Time := 0.000 ns; twdD_F : Time := 0.000 ns; twdCP_R : Time := 0.000 ns; twdCP_F : Time := 0.000 ns);-- synopsys translate_on port( D : in STD_LOGIC; CP : in STD_LOGIC; Q : out STD_LOGIC; QN : out STD_LOGIC);end component;----- Component FD1S -----component FD1S-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen; tpdCP_Q_R : Time := 1.090 ns; tpdCP_Q_F : Time := 1.370 ns; tpdCP_QN_R : Time := 1.590 ns; tpdCP_QN_F : Time := 1.570 ns; tsuD_CP : Time := 1.300 ns; thCP_D : Time := 0.300 ns; tsuTI_CP : Time := 1.300 ns; thCP_TI : Time := 0.300 ns; tsuTE_CP : Time := 1.300 ns; thCP_TE : Time := 0.300 ns; twCP_H : Time := 1.500 ns; twCP_L : Time := 1.500 ns; twdD_R : Time := 0.000 ns; twdD_F : Time := 0.000 ns; twdCP_R : Time := 0.000 ns; twdCP_F : Time := 0.000 ns; twdTI_R : Time := 0.000 ns; twdTI_F : Time := 0.000 ns; twdTE_R : Time := 0.000 ns; twdTE_F : Time := 0.000 ns);-- synopsys translate_on port( D : in STD_LOGIC; CP : in STD_LOGIC; TI : in STD_LOGIC; TE : in STD_LOGIC; Q : out STD_LOGIC; QN : out STD_LOGIC);end component;----- Component FD2 -----component FD2-- synopsys translate_off generic( Timing_mesg: Boolean := Default_Timing_mesg; Timing_xgen: Boolean := Default_Timing_xgen;⌨️ 快捷键说明
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