top.vhd

design compile synthesis user guide

--------------------------------------------------
-- DIGITAL CLOCK CHIP CORE -----------------------
--
-- File: TOP.vhd
-- Task: Top-level block.
--------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity TOP is
  port( SET_TIME,ALARM:in  STD_LOGIC;
        HRS,MINS:in        STD_LOGIC;
        TOGGLE_SWITCH:in   STD_LOGIC;
        CLK:in             STD_LOGIC;
        RESETN:in          STD_LOGIC;
        TEST_MODE:in          STD_LOGIC;
        SPEAKER_OUT:out    STD_LOGIC;
        HR_DISPLAY:out     STD_LOGIC_VECTOR(13 downto 0);
        MIN_DISPLAY:out    STD_LOGIC_VECTOR(13 downto 0);
        AM_PM_OUT:out      STD_LOGIC
  );
end TOP;


architecture NET of TOP is 

  component COMPUTE_BLOCK 
    port( SET_TIME,ALARM:in    STD_LOGIC;
	  HRS,MINS:in          STD_LOGIC;
	  TOGGLE_SWITCH:in     STD_LOGIC;
	  CLK:in 	       STD_LOGIC;
	  RESETN:in            STD_LOGIC;
          TEST_MODE:in         STD_LOGIC;
	  TIM_DISPLAY:out      STD_LOGIC_VECTOR(10 downto 0);
	  ALM_DISPLAY:out      STD_LOGIC_VECTOR(10 downto 0);
	  SPEAKER_OUT:out      STD_LOGIC
    );
  end component;

  component CONVERTOR_CKT
    port( bin_time:in          STD_LOGIC_VECTOR(10 downto 0);
          hr_display:out       STD_LOGIC_VECTOR(13 downto 0);
          min_display:out      STD_LOGIC_VECTOR(13 downto 0);
          am_pm_display:out    STD_LOGIC
    );
  end component;


signal CLK_DISPLAY: STD_LOGIC_VECTOR(10 downto 0);

begin
  U1:COMPUTE_BLOCK
    port map( SET_TIME => SET_TIME,
              ALARM => ALARM,
              HRS => HRS,
              MINS => MINS,
              TOGGLE_SWITCH => TOGGLE_SWITCH,
              CLK => CLK,
              RESETN => RESETN,
              TEST_MODE => TEST_MODE,
              TIM_DISPLAY => CLK_DISPLAY,
              ALM_DISPLAY => CLK_DISPLAY,
              SPEAKER_OUT => SPEAKER_OUT
    );
  U3:CONVERTOR_CKT
    port map( bin_time => CLK_DISPLAY,
              hr_display => HR_DISPLAY,
              min_display => MIN_DISPLAY,
              am_pm_display => AM_PM_OUT
    );
end NET;