top.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 19 行

module TOP ( SET_TIME, ALARM, HRS, MINS, TOGGLE_SWITCH, CLK, RESETN, 
    TEST_MODE, SPEAKER_OUT, HR_DISPLAY, MIN_DISPLAY, AM_PM_OUT );
output [13:0] HR_DISPLAY;
output [13:0] MIN_DISPLAY;
input  SET_TIME, ALARM, HRS, MINS, TOGGLE_SWITCH, CLK, RESETN,TEST_MODE;
output SPEAKER_OUT, AM_PM_OUT;

wand [10:0] CLK_DISPLAY;

    COMPUTE_BLOCK U1 (.SET_TIME(SET_TIME), .ALARM(ALARM), .HRS(HRS), 
        .MINS(MINS), .TOGGLE_SWITCH(TOGGLE_SWITCH), .CLK(CLK), .RESETN(RESETN),
        .TEST_MODE(TEST_MODE), .TIM_DISPLAY(CLK_DISPLAY), 
        .ALM_DISPLAY(CLK_DISPLAY), .SPEAKER_OUT(SPEAKER_OUT) );

    CONVERTOR_CKT U3 (.bin_time(CLK_DISPLAY), .hr_display(HR_DISPLAY), 
        .min_display(MIN_DISPLAY), .am_pm_display(AM_PM_OUT) ); 

endmodule