tb_alarm.vhd

design compile synthesis user guide

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use WORK.conv_pack_top.all;

entity E is
end E;

Architecture A of E is

   signal SET_TIME : std_logic;
   signal    ALARM : std_logic;
   signal      HRS : std_logic;
   signal     MINS : std_logic;
   signal TOGGLE_SWITCH : std_logic;
   signal      CLK : std_logic;
   signal    RESETN : std_logic;
   signal TEST_MODE : std_logic;
   signal SPEAKER_OUT : std_logic;
   signal    HR_DISPLAY : std_logic_vector (13 downto 0);
   signal    MIN_DISPLAY : std_logic_vector (13 downto 0);
   signal    AM_PM_OUT : std_logic;
   signal    test_se : std_logic;
   signal    test_si : std_logic;
   signal    test_so : std_logic;

   component TOP
      Port ( SET_TIME : In    std_logic;  
                ALARM : In    std_logic;
                  HRS : In    std_logic;
                 MINS : In    std_logic;
             TOGGLE_SWITCH : In    std_logic;
                  CLK : In    std_logic;
               RESETN : In    std_logic;
             TEST_MODE : In    std_logic;
             SPEAKER_OUT : Out   std_logic;
             HR_DISPLAY : Out   std_logic_vector (13 downto 0);
             MIN_DISPLAY : Out   std_logic_vector (13 downto 0);
             AM_PM_OUT : Out   std_logic;
             test_se : In   std_logic;
             test_si : In   std_logic;
             test_so : Out   std_logic );
   end component;

begin
   UUT : TOP
      Port Map ( SET_TIME => SET_TIME,
                 ALARM => ALARM,
                 HRS => HRS,
                 MINS => MINS,
                 TOGGLE_SWITCH => TOGGLE_SWITCH,
                 CLK => CLK,
                 RESETN => RESETN,
                 TEST_MODE => TEST_MODE,
                 SPEAKER_OUT => SPEAKER_OUT,
                 HR_DISPLAY => HR_DISPLAY,
                 MIN_DISPLAY => MIN_DISPLAY,
                 AM_PM_OUT => AM_PM_OUT,
                 test_se => test_se,
                 test_si => test_si,
                 test_so => test_so );

-- *** Test Bench - User Defined Section ***
   TB : block

   constant PERIOD : time := 50 ns;
   constant HALF_PERIOD : time := PERIOD / 2;

   signal testbench_done : BOOLEAN := false;

   begin

   CLOCKGEN : process
     begin
     CLK <= '0';
     if (testbench_done) then
        wait;
     else
        wait for HALF_PERIOD;
     end if;
     CLK <= '1';
     wait for HALF_PERIOD;
     end process;

   process begin
      --initialize 
      testbench_done <= false;
      ALARM <= '0';
      HRS <= '0';
      MINS <= '0';
      SET_TIME <= '0';
      TOGGLE_SWITCH <= '0';
      TEST_MODE <= '0';
      test_se <= '0';

      --reset
      RESETN <= '0';
      WAIT FOR 100 ns;
      RESETN <= '1';

      --increment time 65 sec
      WAIT FOR 6500 ns;
      
      -- set alarm to 7:30am
      ALARM <= '1';
      FOR i IN 1 to 7 LOOP
         HRS <= '1';
         WAIT FOR 100 ns;
         HRS <= '0';
         WAIT FOR 100 ns;
      END LOOP;
      FOR i IN 1 to 30 LOOP
         MINS <= '1';
         WAIT FOR 100 ns;
         MINS <= '0';
         WAIT FOR 100 ns;
      END LOOP;
      --aup
      ALARM <= '0';
      
      -- set time to 7:29:50am
      SET_TIME <= '1';
      FOR i IN 1 to 7 LOOP
         HRS <= '1';
         WAIT FOR 100 ns;
         HRS <= '0';
         WAIT FOR 100 ns;
      END LOOP;
      FOR i IN 1 to 27 LOOP
         MINS <= '1';
         WAIT FOR 100 ns;
         MINS <= '0';
         WAIT FOR 100 ns;
      END LOOP;
      SET_TIME <= '0';
      
      -- turn alarm on
      TOGGLE_SWITCH <= not TOGGLE_SWITCH;
      
      -- increment time 65 sec
      WAIT FOR 6500 ns;
      
      -- turn alarm off
      TOGGLE_SWITCH <= not TOGGLE_SWITCH;
      
      -- set time to 11:59:00 am
      SET_TIME <= '1';
      FOR i IN 1 to 4 LOOP
         HRS <= '1';
         WAIT FOR 100 ns;
         HRS <= '0';
         WAIT FOR 100 ns;
      END LOOP;
      FOR i IN 1 to 29 LOOP
         MINS <= '1';
         WAIT FOR 100 ns;
         MINS <= '0';
         WAIT FOR 100 ns;
      END LOOP;
      SET_TIME <= '0';
      
      -- increment time 65 sec
      WAIT FOR 6499 ns;

      testbench_done <= true;
      WAIT;
      end process;
   end block;
-- *** End Test Bench - User Defined Section ***

end A;

configuration TB_ALARM of E is
   for A
      for UUT : TOP
         use entity WORK.TOP (SYN_NET);
      end for;

-- *** User Defined Configuration ***
      for TB
      end for;
-- *** End User Defined Configuration ***

   end for;
end TB_ALARM;