verilog2tds.awk

design compile synthesis user guide

BEGIN{
   verilog = "01x"
   tssi_in = "DUN"
   tssi_out = "LHX"
}


{
   new_line = $1 "	";

   {for (i=1; i<= length($2); i++)
      {
      position = index(verilog,substr($2,i,1))
      new_line = new_line substr(tssi_in,position,1)
      }
   }
 
   {for (i=1; i<= length($3); i++)
      {
      position = index(verilog,substr($3,i,1))
      new_line = new_line substr(tssi_out,position,1)
      }
   }
 
   print new_line
   next;
}