run.scr

design compile synthesis user guide

/* create testsim library */	
read library/class.db
write_testsim_lib class > write_lib.log

/* create testsim model */
read TOP.db
create_testsim_model TOP_testsim.db

/* perform parallel fault simulation of ATPG patterns */
fault_simulate -report_float false -input TOP.vdb -format vdb -output parallel -use_testsim_model TOP_testsim.db

/* report on ATPG coverage results */
restore_test TOP.vdb
report_test -coverage

/* perform serial fault simulation of ATPG patterns */
create_test_clock CLK -period 100 -waveform {45 55}
report_test -testsim_timing
fault_simulate -report_float false -input TOP_0.WGL -format wgl -output serial -use_testsim_model TOP_testsim.db

/* fault simulate verilog functional vectors */
test_default_period = 50
test_default_delay = 0
test_default_strobe = 49
create_test_clock CLK -period 50 -waveform {25 50}
report_test -testsim_timing
fault_simulate -report_float false -input fnc.vec -output fnc -use_testsim_model TOP_testsim.db

/* fault simulate vhdl functional vectors */
test_default_period = 50
test_default_delay = 0
test_default_strobe = 49
create_test_clock CLK -period 50 -waveform {25 50}
report_test -testsim_timing
fault_simulate -report_float false -input fnc.ow -format wif -output fnc -use_testsim_model TOP_testsim.db