compute_block.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 34 行

module COMPUTE_BLOCK ( SET_TIME, ALARM, HRS, MINS, TOGGLE_SWITCH, CLK, RESETN,
                       TEST_MODE, TIM_DISPLAY, ALM_DISPLAY, SPEAKER_OUT );

input SET_TIME, ALARM, HRS, MINS, CLK, RESETN, TOGGLE_SWITCH, TEST_MODE;
output SPEAKER_OUT;
output [10:0] TIM_DISPLAY,ALM_DISPLAY;

wire TIM_AM_PM,ALM_AM_PM,KONNECT12;
wire [3:0] TIM_HRS,ALM_HRS;
wire [5:0] TIM_MINS,ALM_MINS;
reg INT_CLK;

    CLOCK_GEN U7 ( .CLK(CLK), .RESETN(RESETN), .TEST_MODE(TEST_MODE),
        .INT_CLK(INT_CLK) );

    TIME_BLOCK U1 ( .SET_TIME(SET_TIME), .HRS(HRS), .MINS(MINS),  
        .CLK(INT_CLK), .RESETN(RESETN), .ENABLE(!ALARM), 
        .HRS_OUT(TIM_HRS), .MINS_OUT(TIM_MINS), .AM_PM_OUT(TIM_AM_PM), 
        .DISPLAY_BUS(TIM_DISPLAY) );

    ALARM_BLOCK  U2 ( .ALARM(ALARM), .HRS(HRS), .MINS(MINS), 
        .CLK(INT_CLK), .RESETN(RESETN), .ENABLE(ALARM),
        .HRS_OUT(ALM_HRS), .MINS_OUT(ALM_MINS), .AM_PM_OUT(ALM_AM_PM),
        .DISPLAY_BUS(ALM_DISPLAY) );

    COMPARATOR U4 ( .ALARM_HRS(ALM_HRS),.TIME_HRS(TIM_HRS), 
        .ALARM_MINS(ALM_MINS), .TIME_MINS(TIM_MINS),
        .ALARM_AM_PM(ALM_AM_PM), .TIME_AM_PM(TIM_AM_PM), .RINGER(KONNECT12) );

    ALARM_SM_2 U5 ( .COMPARE_IN(KONNECT12), .TOGGLE_ON(TOGGLE_SWITCH), 
        .CLOCK(INT_CLK), .RESETN(RESETN), .RING(SPEAKER_OUT) );

endmodule