.synopsys_dc.setup

design compile synthesis user guide

search_path = ./library + search_path
link_library = {class.db "*"}
target_library = class.db
symbol_library = class.sdb

view_script_submenu_items = \
   {"Remove All Designs","remove_design find(design \"*\")", \
    "Save All Designs", "write find(design \"*\") -out save.db", \
    "set_dont_touch All Designs", "set_dont_touch find(design \"*\")", \
    "Remove dont_touch All Designs", "remove_attribute find(design \"*\") dont_touch"}


compile_fix_multiple_port_nets = true
vhdlout_use_packages = {IEEE.std_logic_1164 class.components}
vhdlout_dont_write_types = "true"
vhdlout_write_components = "false"
insert_test_map_effort_enabled = false