multiply16x16.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 15 行

module Multiply16x16 (op1, op2, res, clk);
/* 16-Bit multiplier */
input [15:0] op1, op2;
output [31:0] res;
input clk;
 
wire [31:0] res_tmp;
reg [31:0] res;
 
always @(posedge clk) begin
   res = res_tmp;
end
assign res_tmp = op1 * op2;
endmodule