comp16.scr

design compile synthesis user guide

/* Script file for constraining Comparator */
rpt_file = "comp16.rpt"
design = "comp16"

current_design Comparator
include script_path + defaults.con

/* Define design environment */
set_load 2.5 cp_out
set_driving_cell -cell FD1 all_inputs()

/* Override auto wire load selection */
set_wire_load 05x05 -mode enclosed

/* Define design constraints */
set_input_delay 1.35 -clock clk_name {ain, bin}
set_output_delay 5.1 -clock clk_name {cp_out}
set_max_area 0

compile 
write -f db -hierarchy -o db_path + design + ".db"
include script_path + report.scr