run.scr

design compile synthesis user guide

/* Initial compile with estimated time-budget 
constraints */
include script_path + initial_compile.scr

current_design ChipLevel
write -hierarchy -out db_path + ChipLevel_init.db

/* Characterize and write_script for all modules */
include script_path + characterize.scr

/* Recompile all modules using write_script 
constraints */
remove_design -all
include script_path + recompile.scr

current_design ChipLevel
write -hierarchy -out db_path + ChipLevel_final.db