uwave.v

design compile synthesis user guide

// This tutorial example is a simple control unit of a microwave oven.
// It comprises of a state machine and two decrementors for counting
// minutes and seconds.

module uwave_ctl (clk, reset, set_time, start_cook, test, cook_time_s,
                  cook_time_m, 
                  cooking, load_8888, load_done, load_clk, min_cook, 
                  sec_cook);

input clk, reset, set_time, start_cook, test; 
input [5:0] cook_time_m;  // cook time set in minutes
input [6:0] cook_time_s;  // cook time set in seconds

output cooking;    // flag for cooking in progress
output load_8888;  // flag for test mode
output load_done;  // flag for cooking completed
output load_clk;   // flag for setting clock
output [5:0] min_cook;  // number of minutes remains in cooking mode
output [6:0] sec_cook;  // number of seconds remains in cooking mode

reg [3:0] outvec;   // same as {cooking, load_8888, load_done, load_clk}
reg [5:0] m_cook_val, min_cook; // minute decrementor value and its reg output
reg [6:0] s_cook_val, sec_cook; // second decrementor value and its reg output
reg [2:0] cur_state, nxt_state;
reg cooking, load_8888, load_done, load_clk;

parameter idle = 3'h0;
parameter timer = 3'h1;
parameter lamp_test = 3'h2;
parameter set_clock = 3'h3;
parameter done_msg = 3'h4;

wire set_hr_min = set_time & ~test;
wire dec_min_sec = ~(| sec_cook) & ( | min_cook);
wire done_cook = ( ~( | min_cook) & ~( | sec_cook)) ;
wire go_cook = ~done_cook & ~test & ~set_time & start_cook;

// Initialization
always @(posedge clk)
  begin
    if (reset) begin
       cooking <= #1 1'b0;
       load_8888 <= #1 1'b0;
       load_done <= #1 1'b0;
       load_clk <= #1 1'b0;
    end
    else begin
       cooking <= #1 outvec[3];
       load_8888 <= #1 outvec[2];
       load_done <= #1 outvec[1];
       load_clk <= #1 outvec[0];
    end
  end

// State machine
always @(posedge clk)
  begin
    if (reset)  cur_state <= idle;	
    else cur_state <= nxt_state;
  end

always @(cur_state or set_hr_min or done_cook or test or go_cook)
  begin
    nxt_state <= idle;
    outvec <= 4'b0000;
    case(cur_state)
      idle: begin
              if (test) begin
                 nxt_state <= lamp_test;
                 outvec <= 4'b0100;
              end
              else if (go_cook) begin
                 nxt_state <= timer;
                 outvec <= 4'b1000;
              end
              else if (set_hr_min) begin
                 nxt_state <= set_clock;
                 outvec <= 4'b0001;
              end
            end

      timer: begin
               if (done_cook) begin
                  nxt_state <= done_msg;
                  outvec <= 4'b0010;
               end
               else begin
                  nxt_state <= timer;
                  outvec <= 4'b1000;
               end
             end

      lamp_test: outvec <= 4'b0100;
 
      set_clock: outvec <= 4'b0001;
 
      done_msg:  outvec <= 4'b0010;

    endcase
  end

always @(posedge clk)
  begin
       min_cook <= #1 m_cook_val;
       sec_cook <= #1 s_cook_val;
  end 

// Decrementing cook time in seconds
always @(start_cook or sec_cook or cook_time_s or cooking or dec_min_sec)
  begin
    if (start_cook) begin
       s_cook_val <= cook_time_s;
    end
    else if (cooking) begin
       if (dec_min_sec) begin
          s_cook_val <= 7'b0111011;
       end
       else begin
          s_cook_val <= sec_cook - 1;
       end
    end
    else begin
       s_cook_val <= 7'h0;
    end
  end
 
// Decrementing cook time in minutes
always @(start_cook or min_cook or cook_time_m or cooking or dec_min_sec)
  begin
    if (start_cook) begin
       m_cook_val <= cook_time_m;
    end
    else if (cooking) begin
       if (dec_min_sec) begin
          m_cook_val <= min_cook - 1;
       end
       else begin
          m_cook_val <= min_cook;
       end
    end
    else begin
       m_cook_val <= 6'h0;
    end
  end

endmodule