alarm_sm_2.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 38 行

entity ALARM_SM_2 is 
	port(COMPARE_IN,TOGGLE_ON : in bit;
             CLOCK: in bit;
	     RING : out bit);
end;

architecture BEHAVIOR of ALARM_SM_2 is 
	type state_type is (IDLE, ACTIVATE);
	signal CURRENT_STATE, NEXT_STATE: state_type;
begin
	COMBIN: process(CURRENT_STATE,COMPARE_IN,TOGGLE_ON)
	begin
	case CURRENT_STATE is 
		when IDLE =>
			RING <= '0';
			if (COMPARE_IN and TOGGLE_ON) = '1' then
				NEXT_STATE <= ACTIVATE;
			else
				NEXT_STATE <= IDLE;
			end if;

		when ACTIVATE =>
			RING <= '1';
			if TOGGLE_ON = '0' then
				NEXT_STATE <= IDLE;
			else
				NEXT_STATE <= ACTIVATE;
			end if;
	end case;
	end process;

	SYNCH: process
	begin
	wait until CLOCK' event and CLOCK = '1';
	CURRENT_STATE <= NEXT_STATE;
	end process;
end BEHAVIOR;